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+/*
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+ * MikroTik SPI-NOR RouterBOARDs support
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+ *
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+ * - MikroTik RouterBOARD mAP L-2nD
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+ *
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+ * Copyright (C) 2017 Thibaut VARENE <[email protected]>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include <linux/platform_device.h>
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+#include <linux/phy.h>
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+#include <linux/routerboot.h>
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+#include <linux/gpio.h>
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+
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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+
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+#include <asm/prom.h>
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+#include <asm/mach-ath79/ath79.h>
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+
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+#include "common.h"
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+#include "dev-eth.h"
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+#include "dev-spi.h"
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+#include "dev-gpio-buttons.h"
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+#include "dev-leds-gpio.h"
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+#include "dev-m25p80.h"
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+#include "dev-usb.h"
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+#include "dev-wmac.h"
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+#include "machtypes.h"
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+#include "routerboot.h"
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+
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+#define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
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+#define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
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+
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+#define RBSPI_HAS_USB BIT(0)
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+#define RBSPI_HAS_WLAN BIT(1)
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+#define RBSPI_HAS_WAN4 BIT(2) /* has WAN port on PHY4 */
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+
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+#define RB_ROUTERBOOT_OFFSET 0x0000
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+#define RB_BIOS_SIZE 0x1000
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+#define RB_SOFT_CFG_SIZE 0x1000
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+#define RB_KERNEL_SIZE (2 * 1024 * 1024) /* 2MB kernel */
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+
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+/* Flash partitions indexes */
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+enum {
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+ RBSPI_PART_RBOOT,
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+ RBSPI_PART_HCONF,
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+ RBSPI_PART_BIOS,
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+ RBSPI_PART_RBOOT2,
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+ RBSPI_PART_SCONF,
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+ RBSPI_PART_KERN,
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+ RBSPI_PART_ROOT,
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+ RBSPI_PARTS
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+};
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+
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+static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
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+
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+/*
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+ * Setup the SPI flash partition table based on initial parsing.
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+ * The kernel can be at any aligned position and have any size.
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+ * The size of the kernel partition is the desired RB_KERNEL_SIZE
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+ * minus the size of the preceding partitions (128KB).
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+ */
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+static void __init rbspi_init_partitions(const struct rb_info *info)
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+{
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+ struct mtd_partition *parts = rbspi_spi_partitions;
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+ memset(parts, 0x0, sizeof(*parts));
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+
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+ parts[RBSPI_PART_RBOOT].name = "routerboot";
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+ parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
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+ parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
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+ parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
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+
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+ parts[RBSPI_PART_HCONF].name = "hard_config";
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+ parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
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+ parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
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+ parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
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+
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+ parts[RBSPI_PART_BIOS].name = "bios";
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+ parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
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+ + info->hard_cfg_size;
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+ parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
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+ parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
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+
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+ parts[RBSPI_PART_RBOOT2].name = "routerboot2";
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+ parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
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+ + RB_BIOS_SIZE;
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+ parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
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+ - parts[RBSPI_PART_RBOOT2].offset;
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+ parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
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+
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+ parts[RBSPI_PART_SCONF].name = "soft_config";
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+ parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
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+ parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
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+
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+ parts[RBSPI_PART_KERN].name = "kernel";
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+ parts[RBSPI_PART_KERN].offset = parts[RBSPI_PART_SCONF].offset
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+ + parts[RBSPI_PART_SCONF].size;
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+ parts[RBSPI_PART_KERN].size = RB_KERNEL_SIZE
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+ - parts[RBSPI_PART_KERN].offset;
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+
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+ parts[RBSPI_PART_ROOT].name = "rootfs";
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+ parts[RBSPI_PART_ROOT].offset = parts[RBSPI_PART_KERN].offset
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+ + parts[RBSPI_PART_KERN].size;
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+ parts[RBSPI_PART_ROOT].size = MTDPART_SIZ_FULL;
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+}
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+
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+static struct flash_platform_data rbspi_spi_flash_data = {
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+ .parts = rbspi_spi_partitions,
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+ .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
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+};
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+
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+/* Several boards only have a single reset button wired to GPIO 16 */
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+#define RBSPI_GPIO_BTN_RESET16 16
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+
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+static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
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+ {
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+ .desc = "Reset button",
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+ .type = EV_KEY,
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+ .code = KEY_RESTART,
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+ .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
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+ .gpio = RBSPI_GPIO_BTN_RESET16,
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+ .active_low = 1,
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+ },
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+};
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+
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+/* RB mAP L-2nD gpios */
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+#define RBMAPL_GPIO_LED_POWER 17
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+#define RBMAPL_GPIO_LED_USER 14
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+#define RBMAPL_GPIO_LED_ETH 4
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+#define RBMAPL_GPIO_LED_WLAN 11
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+
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+static struct gpio_led rbmapl_leds[] __initdata = {
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+ {
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+ .name = "rb:green:power",
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+ .gpio = RBMAPL_GPIO_LED_POWER,
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+ .active_low = 0,
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+ .default_state = LEDS_GPIO_DEFSTATE_ON,
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+ }, {
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+ .name = "rb:green:user",
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+ .gpio = RBMAPL_GPIO_LED_USER,
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+ .active_low = 0,
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+ }, {
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+ .name = "rb:green:eth",
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+ .gpio = RBMAPL_GPIO_LED_ETH,
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+ .active_low = 0,
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+ }, {
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+ .name = "rb:green:wlan",
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+ .gpio = RBMAPL_GPIO_LED_WLAN,
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+ .active_low = 0,
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+ },
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+};
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+
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+void __init rbspi_wlan_init(int wmac_offset)
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+{
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+ char *art_buf;
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+ u8 wlan_mac[ETH_ALEN];
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+
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+ art_buf = rb_get_wlan_data();
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+ if (!art_buf)
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+ return;
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+
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+ ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
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+ ath79_register_wmac(art_buf + 0x1000, wlan_mac);
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+
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+ kfree(art_buf);
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+}
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+
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+/*
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+ * Common platform init routine for all SPI NOR devices.
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+ */
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+static int __init rbspi_platform_setup(void)
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+{
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+ const struct rb_info *info;
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+ char buf[64];
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+
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+ info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
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+ if (!info)
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+ return -ENODEV;
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+
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+ scnprintf(buf, sizeof(buf), "MikroTik %s",
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+ (info->board_name) ? info->board_name : "");
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+ mips_set_machine_name(buf);
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+
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+ /* fix partitions based on flash parsing */
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+ rbspi_init_partitions(info);
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+
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+ return 0;
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+}
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+
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+/*
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+ * Common peripherals init routine for all SPI NOR devices.
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+ * Sets SPI and USB.
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+ */
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+static void __init rbspi_peripherals_setup(u32 flags)
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+{
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+ ath79_register_m25p80(&rbspi_spi_flash_data);
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+
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+ if (flags & RBSPI_HAS_USB)
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+ ath79_register_usb();
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+}
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+
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+/*
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+ * Common network init routine for all SPI NOR devices.
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+ * Sets LAN/WAN/WLAN.
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+ */
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+static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
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+ int wmac_offset)
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+{
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+ /* for QCA953x that will init mdio1_device/data */
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+ ath79_register_mdio(0, 0x0);
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+
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+ if (flags & RBSPI_HAS_WAN4) {
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+ ath79_setup_ar934x_eth_cfg(0);
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+
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+ /* set switch to oper mode 1, PHY4 connected to CPU */
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+ ath79_switch_data.phy4_mii_en = 1;
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+ ath79_switch_data.phy_poll_mask |= BIT(4);
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+
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+ /* init GMAC0 connected to PHY4 at 100M */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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+ ath79_eth0_data.phy_mask = BIT(4);
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+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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+ ath79_register_eth(0);
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+ } else {
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+ /* set the SoC to SW_ONLY_MODE, which connects all PHYs
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+ * to the internal switch.
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+ * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
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+ * the QCA953x, this works because this configuration bit is
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+ * the same as the AR934x. There's no equivalent function for
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+ * QCA953x for now. */
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+ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
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+ }
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+
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+ /* init GMAC1 */
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+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
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+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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+ ath79_register_eth(1);
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+
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+ if (flags & RBSPI_HAS_WLAN)
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+ rbspi_wlan_init(wmac_offset);
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+}
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+
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+/*
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+ * Init the mAP lite hardware.
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+ * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
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+ * Trying to use GMAC0 in direct mode was unsucessful, so we're
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+ * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
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+ * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
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+ */
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+static void __init rbmapl_setup(void)
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+{
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+ u32 flags = RBSPI_HAS_WLAN;
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+
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+ if (rbspi_platform_setup())
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+ return;
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+
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+ rbspi_peripherals_setup(flags);
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+
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+ /* GMAC1 is HW MAC, WLAN MAC is HW MAC + 1 */
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+ rbspi_network_setup(flags, 0, 1);
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+
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+ ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
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+
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+ /* mAP lite has a single reset button as gpio 16 */
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+ ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
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+ ARRAY_SIZE(rbspi_gpio_keys_reset16),
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+ rbspi_gpio_keys_reset16);
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+
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+ /* clear internal multiplexing */
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+ ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
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+ ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
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+}
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+
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+MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
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