bcm53xx: add arm l2c overwrite options like in mainline kernel

Instead of setting the l2c_aux_val variable in the board code make it
possible to set these through device tree and make use of that.

Signed-off-by: Hauke Mehrtens <[email protected]>

SVN-Revision: 46129

target/linux/bcm53xx/patches-4.1/070-ARM-l2c-restore-the-behaviour-documented-above-l2c_e.patch

@@ -0,0 +1,43 @@
+From d965b0fca7dcde3f82c982e0bf1631069fdeb8c9 Mon Sep 17 00:00:00 2001
+From: Russell King <[email protected]>
+Date: Fri, 15 May 2015 11:56:45 +0100
+Subject: [PATCH 70/74] ARM: l2c: restore the behaviour documented above
+ l2c_enable()
+
+l2c_enable() is documented that it must not be called if the cache has
+already been enabled.  Unfortunately, commit 6b49241ac252 ("ARM: 8259/1:
+l2c: Refactor the driver to use commit-like interface") changed this
+without updating the comment, for very little reason.  Revert this
+change and restore the expected behaviour.
+
+Signed-off-by: Russell King <[email protected]>
+---
+ arch/arm/mm/cache-l2x0.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/arm/mm/cache-l2x0.c
++++ b/arch/arm/mm/cache-l2x0.c
+@@ -129,10 +129,6 @@ static void l2c_enable(void __iomem *bas
+ {
+ 	unsigned long flags;
+ 
+-	/* Do not touch the controller if already enabled. */
+-	if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)
+-		return;
+-
+ 	l2x0_saved_regs.aux_ctrl = aux;
+ 	l2c_configure(base);
+ 
+@@ -163,7 +159,11 @@ static void l2c_save(void __iomem *base)
+ 
+ static void l2c_resume(void)
+ {
+-	l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
++	void __iomem *base = l2x0_base;
++
++	/* Do not touch the controller if already enabled. */
++	if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
++		l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
+ }
+ 
+ /*

target/linux/bcm53xx/patches-4.1/071-ARM-l2c-write-auxiliary-control-register-first.patch

@@ -0,0 +1,30 @@
+From 7705dd256ce363f8b01429efb2f0dc4d1ee23c89 Mon Sep 17 00:00:00 2001
+From: Russell King <[email protected]>
+Date: Fri, 15 May 2015 11:07:14 +0100
+Subject: [PATCH 71/74] ARM: l2c: write auxiliary control register first
+
+Before calling the controller specific configuration function, write
+the auxiliary control register first, so that bits shared with other
+registers (such as the prefetch control register) are not overwritten
+by the later write to the auxctrl register.
+
+Signed-off-by: Russell King <[email protected]>
+---
+ arch/arm/mm/cache-l2x0.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/mm/cache-l2x0.c
++++ b/arch/arm/mm/cache-l2x0.c
+@@ -115,10 +115,10 @@ static void l2c_configure(void __iomem *
+ 		return;
+ 	}
+ 
++	l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
++
+ 	if (l2x0_data->configure)
+ 		l2x0_data->configure(base);
+-
+-	l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+ }
+ 
+ /*

target/linux/bcm53xx/patches-4.1/072-ARM-l2c-clean-up-l2c_configure.patch

@@ -0,0 +1,109 @@
+From 50beefde30224888d6d63224405ace4bdd4b32a0 Mon Sep 17 00:00:00 2001
+From: Russell King <[email protected]>
+Date: Fri, 15 May 2015 11:05:54 +0100
+Subject: [PATCH 72/74] ARM: l2c: clean up l2c_configure()
+
+l2c_configure() does not follow the pattern of other l2c_* functions.
+Fix this so that it does to avoid future confusion.
+
+Signed-off-by: Russell King <[email protected]>
+---
+ arch/arm/mm/cache-l2x0.c | 23 ++++++++++++++---------
+ 1 file changed, 14 insertions(+), 9 deletions(-)
+
+--- a/arch/arm/mm/cache-l2x0.c
++++ b/arch/arm/mm/cache-l2x0.c
+@@ -110,15 +110,7 @@ static inline void l2c_unlock(void __iom
+ 
+ static void l2c_configure(void __iomem *base)
+ {
+-	if (outer_cache.configure) {
+-		outer_cache.configure(&l2x0_saved_regs);
+-		return;
+-	}
+-
+ 	l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+-
+-	if (l2x0_data->configure)
+-		l2x0_data->configure(base);
+ }
+ 
+ /*
+@@ -130,7 +122,11 @@ static void l2c_enable(void __iomem *bas
+ 	unsigned long flags;
+ 
+ 	l2x0_saved_regs.aux_ctrl = aux;
+-	l2c_configure(base);
++
++	if (outer_cache.configure)
++		outer_cache.configure(&l2x0_saved_regs);
++	else
++		l2x0_data->configure(base);
+ 
+ 	l2c_unlock(base, num_lock);
+ 
+@@ -252,6 +248,7 @@ static const struct l2c_init_data l2c210
+ 	.num_lock = 1,
+ 	.enable = l2c_enable,
+ 	.save = l2c_save,
++	.configure = l2c_configure,
+ 	.outer_cache = {
+ 		.inv_range = l2c210_inv_range,
+ 		.clean_range = l2c210_clean_range,
+@@ -409,6 +406,7 @@ static const struct l2c_init_data l2c220
+ 	.num_lock = 1,
+ 	.enable = l2c220_enable,
+ 	.save = l2c_save,
++	.configure = l2c_configure,
+ 	.outer_cache = {
+ 		.inv_range = l2c220_inv_range,
+ 		.clean_range = l2c220_clean_range,
+@@ -569,6 +567,8 @@ static void l2c310_configure(void __iome
+ {
+ 	unsigned revision;
+ 
++	l2c_configure(base);
++
+ 	/* restore pl310 setup */
+ 	l2c_write_sec(l2x0_saved_regs.tag_latency, base,
+ 		      L310_TAG_LATENCY_CTRL);
+@@ -1066,6 +1066,7 @@ static const struct l2c_init_data of_l2c
+ 	.of_parse = l2x0_of_parse,
+ 	.enable = l2c_enable,
+ 	.save = l2c_save,
++	.configure = l2c_configure,
+ 	.outer_cache = {
+ 		.inv_range   = l2c210_inv_range,
+ 		.clean_range = l2c210_clean_range,
+@@ -1084,6 +1085,7 @@ static const struct l2c_init_data of_l2c
+ 	.of_parse = l2x0_of_parse,
+ 	.enable = l2c220_enable,
+ 	.save = l2c_save,
++	.configure = l2c_configure,
+ 	.outer_cache = {
+ 		.inv_range   = l2c220_inv_range,
+ 		.clean_range = l2c220_clean_range,
+@@ -1416,6 +1418,7 @@ static const struct l2c_init_data of_aur
+ 	.enable = l2c_enable,
+ 	.fixup = aurora_fixup,
+ 	.save  = aurora_save,
++	.configure = l2c_configure,
+ 	.outer_cache = {
+ 		.inv_range   = aurora_inv_range,
+ 		.clean_range = aurora_clean_range,
+@@ -1435,6 +1438,7 @@ static const struct l2c_init_data of_aur
+ 	.enable = aurora_enable_no_outer,
+ 	.fixup = aurora_fixup,
+ 	.save  = aurora_save,
++	.configure = l2c_configure,
+ 	.outer_cache = {
+ 		.resume      = l2c_resume,
+ 	},
+@@ -1608,6 +1612,7 @@ static void __init tauros3_save(void __i
+ 
+ static void tauros3_configure(void __iomem *base)
+ {
++	l2c_configure(base);
+ 	writel_relaxed(l2x0_saved_regs.aux2_ctrl,
+ 		       base + TAUROS3_AUX2_CTRL);
+ 	writel_relaxed(l2x0_saved_regs.prefetch_ctrl,

target/linux/bcm53xx/patches-4.1/073-ARM-l2c-only-unlock-caches-if-NS_LOCKDOWN-bit-is-set.patch

@@ -0,0 +1,149 @@
+From e946a8cbe4a47a7c2615ffb0d45712e72c7d0f3a Mon Sep 17 00:00:00 2001
+From: Russell King <[email protected]>
+Date: Fri, 15 May 2015 11:51:51 +0100
+Subject: [PATCH 73/74] ARM: l2c: only unlock caches if NS_LOCKDOWN bit is set
+
+Some L2C caches have a bit which allows non-secure software to control
+the cache lockdown.  Some platforms are unable to set this bit.  To
+avoid receiving an abort while trying to unlock the cache lines, check
+the state of this bit before unlocking.  We do this by providing a new
+method in the l2c_init_data to perform the unlocking.
+
+Signed-off-by: Russell King <[email protected]>
+---
+ arch/arm/mm/cache-l2x0.c | 26 +++++++++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/mm/cache-l2x0.c
++++ b/arch/arm/mm/cache-l2x0.c
+@@ -42,6 +42,7 @@ struct l2c_init_data {
+ 	void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
+ 	void (*save)(void __iomem *);
+ 	void (*configure)(void __iomem *);
++	void (*unlock)(void __iomem *, unsigned);
+ 	struct outer_cache_fns outer_cache;
+ };
+ 
+@@ -128,7 +129,7 @@ static void l2c_enable(void __iomem *bas
+ 	else
+ 		l2x0_data->configure(base);
+ 
+-	l2c_unlock(base, num_lock);
++	l2x0_data->unlock(base, num_lock);
+ 
+ 	local_irq_save(flags);
+ 	__l2c_op_way(base + L2X0_INV_WAY);
+@@ -249,6 +250,7 @@ static const struct l2c_init_data l2c210
+ 	.enable = l2c_enable,
+ 	.save = l2c_save,
+ 	.configure = l2c_configure,
++	.unlock = l2c_unlock,
+ 	.outer_cache = {
+ 		.inv_range = l2c210_inv_range,
+ 		.clean_range = l2c210_clean_range,
+@@ -400,6 +402,12 @@ static void l2c220_enable(void __iomem *
+ 	l2c_enable(base, aux, num_lock);
+ }
+ 
++static void l2c220_unlock(void __iomem *base, unsigned num_lock)
++{
++	if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN)
++		l2c_unlock(base, num_lock);
++}
++
+ static const struct l2c_init_data l2c220_data = {
+ 	.type = "L2C-220",
+ 	.way_size_0 = SZ_8K,
+@@ -407,6 +415,7 @@ static const struct l2c_init_data l2c220
+ 	.enable = l2c220_enable,
+ 	.save = l2c_save,
+ 	.configure = l2c_configure,
++	.unlock = l2c220_unlock,
+ 	.outer_cache = {
+ 		.inv_range = l2c220_inv_range,
+ 		.clean_range = l2c220_clean_range,
+@@ -755,6 +764,12 @@ static void l2c310_resume(void)
+ 		set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
+ }
+ 
++static void l2c310_unlock(void __iomem *base, unsigned num_lock)
++{
++	if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN)
++		l2c_unlock(base, num_lock);
++}
++
+ static const struct l2c_init_data l2c310_init_fns __initconst = {
+ 	.type = "L2C-310",
+ 	.way_size_0 = SZ_8K,
+@@ -763,6 +778,7 @@ static const struct l2c_init_data l2c310
+ 	.fixup = l2c310_fixup,
+ 	.save = l2c310_save,
+ 	.configure = l2c310_configure,
++	.unlock = l2c310_unlock,
+ 	.outer_cache = {
+ 		.inv_range = l2c210_inv_range,
+ 		.clean_range = l2c210_clean_range,
+@@ -1067,6 +1083,7 @@ static const struct l2c_init_data of_l2c
+ 	.enable = l2c_enable,
+ 	.save = l2c_save,
+ 	.configure = l2c_configure,
++	.unlock = l2c_unlock,
+ 	.outer_cache = {
+ 		.inv_range   = l2c210_inv_range,
+ 		.clean_range = l2c210_clean_range,
+@@ -1086,6 +1103,7 @@ static const struct l2c_init_data of_l2c
+ 	.enable = l2c220_enable,
+ 	.save = l2c_save,
+ 	.configure = l2c_configure,
++	.unlock = l2c220_unlock,
+ 	.outer_cache = {
+ 		.inv_range   = l2c220_inv_range,
+ 		.clean_range = l2c220_clean_range,
+@@ -1213,6 +1231,7 @@ static const struct l2c_init_data of_l2c
+ 	.fixup = l2c310_fixup,
+ 	.save  = l2c310_save,
+ 	.configure = l2c310_configure,
++	.unlock = l2c310_unlock,
+ 	.outer_cache = {
+ 		.inv_range   = l2c210_inv_range,
+ 		.clean_range = l2c210_clean_range,
+@@ -1242,6 +1261,7 @@ static const struct l2c_init_data of_l2c
+ 	.fixup = l2c310_fixup,
+ 	.save  = l2c310_save,
+ 	.configure = l2c310_configure,
++	.unlock = l2c310_unlock,
+ 	.outer_cache = {
+ 		.inv_range   = l2c210_inv_range,
+ 		.clean_range = l2c210_clean_range,
+@@ -1419,6 +1439,7 @@ static const struct l2c_init_data of_aur
+ 	.fixup = aurora_fixup,
+ 	.save  = aurora_save,
+ 	.configure = l2c_configure,
++	.unlock = l2c_unlock,
+ 	.outer_cache = {
+ 		.inv_range   = aurora_inv_range,
+ 		.clean_range = aurora_clean_range,
+@@ -1439,6 +1460,7 @@ static const struct l2c_init_data of_aur
+ 	.fixup = aurora_fixup,
+ 	.save  = aurora_save,
+ 	.configure = l2c_configure,
++	.unlock = l2c_unlock,
+ 	.outer_cache = {
+ 		.resume      = l2c_resume,
+ 	},
+@@ -1589,6 +1611,7 @@ static const struct l2c_init_data of_bcm
+ 	.enable = l2c310_enable,
+ 	.save  = l2c310_save,
+ 	.configure = l2c310_configure,
++	.unlock = l2c310_unlock,
+ 	.outer_cache = {
+ 		.inv_range   = bcm_inv_range,
+ 		.clean_range = bcm_clean_range,
+@@ -1626,6 +1649,7 @@ static const struct l2c_init_data of_tau
+ 	.enable = l2c_enable,
+ 	.save  = tauros3_save,
+ 	.configure = tauros3_configure,
++	.unlock = l2c_unlock,
+ 	/* Tauros3 broadcasts L1 cache operations to L2 */
+ 	.outer_cache = {
+ 		.resume      = l2c_resume,

target/linux/bcm53xx/patches-4.1/074-ARM-l2c-avoid-passing-auxiliary-control-register-thr.patch

@@ -0,0 +1,129 @@
+From 5b290ec2074c68b9f4f8f8789fa9b3e1782869e7 Mon Sep 17 00:00:00 2001
+From: Russell King <[email protected]>
+Date: Fri, 15 May 2015 12:03:29 +0100
+Subject: [PATCH 74/74] ARM: l2c: avoid passing auxiliary control register
+ through enable method
+
+Avoid passing the auxiliary control register value through the enable
+method.  In the resume path, we have to read the value stored in
+l2x0_saved_regs.aux_ctrl, only to have it immediately written back by
+l2c_enable().  We can avoid this if we have __l2c_init() save the value
+directly to l2x0_saved_regs.aux_ctrl before calling the specific enable
+method.
+
+Signed-off-by: Russell King <[email protected]>
+---
+ arch/arm/mm/cache-l2x0.c | 32 +++++++++++++++++---------------
+ 1 file changed, 17 insertions(+), 15 deletions(-)
+
+--- a/arch/arm/mm/cache-l2x0.c
++++ b/arch/arm/mm/cache-l2x0.c
+@@ -38,7 +38,7 @@ struct l2c_init_data {
+ 	unsigned way_size_0;
+ 	unsigned num_lock;
+ 	void (*of_parse)(const struct device_node *, u32 *, u32 *);
+-	void (*enable)(void __iomem *, u32, unsigned);
++	void (*enable)(void __iomem *, unsigned);
+ 	void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
+ 	void (*save)(void __iomem *);
+ 	void (*configure)(void __iomem *);
+@@ -118,12 +118,10 @@ static void l2c_configure(void __iomem *
+  * Enable the L2 cache controller.  This function must only be
+  * called when the cache controller is known to be disabled.
+  */
+-static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
++static void l2c_enable(void __iomem *base, unsigned num_lock)
+ {
+ 	unsigned long flags;
+ 
+-	l2x0_saved_regs.aux_ctrl = aux;
+-
+ 	if (outer_cache.configure)
+ 		outer_cache.configure(&l2x0_saved_regs);
+ 	else
+@@ -160,7 +158,7 @@ static void l2c_resume(void)
+ 
+ 	/* Do not touch the controller if already enabled. */
+ 	if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
+-		l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
++		l2c_enable(base, l2x0_data->num_lock);
+ }
+ 
+ /*
+@@ -390,16 +388,16 @@ static void l2c220_sync(void)
+ 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ }
+ 
+-static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock)
++static void l2c220_enable(void __iomem *base, unsigned num_lock)
+ {
+ 	/*
+ 	 * Always enable non-secure access to the lockdown registers -
+ 	 * we write to them as part of the L2C enable sequence so they
+ 	 * need to be accessible.
+ 	 */
+-	aux |= L220_AUX_CTRL_NS_LOCKDOWN;
++	l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN;
+ 
+-	l2c_enable(base, aux, num_lock);
++	l2c_enable(base, num_lock);
+ }
+ 
+ static void l2c220_unlock(void __iomem *base, unsigned num_lock)
+@@ -612,10 +610,11 @@ static int l2c310_cpu_enable_flz(struct
+ 	return NOTIFY_OK;
+ }
+ 
+-static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
++static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
+ {
+ 	unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
+ 	bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
++	u32 aux = l2x0_saved_regs.aux_ctrl;
+ 
+ 	if (rev >= L310_CACHE_ID_RTL_R2P0) {
+ 		if (cortex_a9) {
+@@ -658,9 +657,9 @@ static void __init l2c310_enable(void __
+ 	 * we write to them as part of the L2C enable sequence so they
+ 	 * need to be accessible.
+ 	 */
+-	aux |= L310_AUX_CTRL_NS_LOCKDOWN;
++	l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN;
+ 
+-	l2c_enable(base, aux, num_lock);
++	l2c_enable(base, num_lock);
+ 
+ 	/* Read back resulting AUX_CTRL value as it could have been altered. */
+ 	aux = readl_relaxed(base + L2X0_AUX_CTRL);
+@@ -872,8 +871,11 @@ static int __init __l2c_init(const struc
+ 	 * Check if l2x0 controller is already enabled.  If we are booting
+ 	 * in non-secure mode accessing the below registers will fault.
+ 	 */
+-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
+-		data->enable(l2x0_base, aux, data->num_lock);
++	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
++		l2x0_saved_regs.aux_ctrl = aux;
++
++		data->enable(l2x0_base, data->num_lock);
++	}
+ 
+ 	outer_cache = fns;
+ 
+@@ -1388,7 +1390,7 @@ static void aurora_save(void __iomem *ba
+  * For Aurora cache in no outer mode, enable via the CP15 coprocessor
+  * broadcasting of cache commands to L2.
+  */
+-static void __init aurora_enable_no_outer(void __iomem *base, u32 aux,
++static void __init aurora_enable_no_outer(void __iomem *base,
+ 	unsigned num_lock)
+ {
+ 	u32 u;
+@@ -1399,7 +1401,7 @@ static void __init aurora_enable_no_oute
+ 
+ 	isb();
+ 
+-	l2c_enable(base, aux, num_lock);
++	l2c_enable(base, num_lock);
+ }
+ 
+ static void __init aurora_fixup(void __iomem *base, u32 cache_id,

target/linux/bcm53xx/patches-4.1/075-ARM-8391-1-l2c-add-options-to-overwrite-prefetching-.patch

@@ -0,0 +1,60 @@
+From ec3bd0e68a679a7af2c46af1ddc9af8b534a8b0e Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <[email protected]>
+Date: Wed, 10 Jun 2015 20:23:24 +0100
+Subject: [PATCH] ARM: 8391/1: l2c: add options to overwrite prefetching
+ behavior
+
+These options make it possible to overwrites the data and instruction
+prefetching behavior of the arm pl310 cache controller.
+
+Signed-off-by: Hauke Mehrtens <[email protected]>
+Acked-by: Florian Fainelli <[email protected]>
+Signed-off-by: Russell King <[email protected]>
+---
+ Documentation/devicetree/bindings/arm/l2cc.txt |  5 +++++
+ arch/arm/mm/cache-l2x0.c                       | 20 ++++++++++++++++++++
+ 2 files changed, 25 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/l2cc.txt
++++ b/Documentation/devicetree/bindings/arm/l2cc.txt
+@@ -67,6 +67,11 @@ Optional properties:
+   disable if zero.
+ - arm,prefetch-offset : Override prefetch offset value. Valid values are
+   0-7, 15, 23, and 31.
++- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
++  (forcibly enable), property absent (retain settings set by firmware)
++- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
++  <1> (forcibly enable), property absent (retain settings set by
++  firmware)
+ 
+ Example:
+ 
+--- a/arch/arm/mm/cache-l2x0.c
++++ b/arch/arm/mm/cache-l2x0.c
+@@ -1221,6 +1221,26 @@ static void __init l2c310_of_parse(const
+ 		pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n");
+ 	}
+ 
++	ret = of_property_read_u32(np, "prefetch-data", &val);
++	if (ret == 0) {
++		if (val)
++			prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH;
++		else
++			prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH;
++	} else if (ret != -EINVAL) {
++		pr_err("L2C-310 OF prefetch-data property value is missing\n");
++	}
++
++	ret = of_property_read_u32(np, "prefetch-instr", &val);
++	if (ret == 0) {
++		if (val)
++			prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH;
++		else
++			prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH;
++	} else if (ret != -EINVAL) {
++		pr_err("L2C-310 OF prefetch-instr property value is missing\n");
++	}
++
+ 	l2x0_saved_regs.prefetch_ctrl = prefetch;
+ }
+ 

target/linux/bcm53xx/patches-4.1/077-ARM-l2c-Add-support-for-the-arm-shared-override-prop.patch

@@ -0,0 +1,81 @@
+From 1bc7c02e7f37ddfa09cb0db330ee8cd4034d6410 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <[email protected]>
+Date: Thu, 7 May 2015 11:27:11 +0200
+Subject: [PATCH 1/4] ARM: l2c: Add support for the "arm, shared-override"
+ property
+
+"CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
+Shareable attribute" states:
+
+    "The default behavior of the cache controller with respect to the
+     shareable attribute is to transform Normal Memory Non-cacheable
+     transactions into:
+        - cacheable no allocate for reads
+        - write through no write allocate for writes."
+
+Depending on the system architecture, this may cause memory corruption
+in the presence of bus mastering devices (e.g. OHCI). To avoid such
+corruption, the default behavior can be disabled by setting the Shared
+Override bit in the Auxiliary Control register.
+
+Currently the Shared Override bit can be set only using C code:
+  - by calling l2x0_init() directly, which is deprecated,
+  - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
+    fields, but using values differing from 0/~0 is also deprecated.
+
+Hence add support for an "arm,shared-override" device tree property for
+the l2c device node. By specifying this property, affected systems can
+indicate that non-cacheable transactions must not be transformed.
+Then, it's up to the OS to decide. The current behavior is to set the
+"shared attribute override enable" bit, as there may exist kernel linear
+mappings and cacheable aliases for the DMA buffers, even if CMA is
+enabled.
+
+See also commit 1a8e41cd672f894b ("ARM: 6395/1: VExpress: Set bit 22 in
+the PL310 (cache controller) AuxCtlr register"):
+
+    "Clearing bit 22 in the PL310 Auxiliary Control register (shared
+     attribute override enable) has the side effect of transforming
+     Normal Shared Non-cacheable reads into Cacheable no-allocate reads.
+
+     Coherent DMA buffers in Linux always have a Cacheable alias via the
+     kernel linear mapping and the processor can speculatively load
+     cache lines into the PL310 controller. With bit 22 cleared,
+     Non-cacheable reads would unexpectedly hit such cache lines leading
+     to buffer corruption."
+
+Signed-off-by: Geert Uytterhoeven <[email protected]>
+---
+ Documentation/devicetree/bindings/arm/l2cc.txt | 6 ++++++
+ arch/arm/mm/cache-l2x0.c                       | 5 +++++
+ 2 files changed, 11 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/l2cc.txt
++++ b/Documentation/devicetree/bindings/arm/l2cc.txt
+@@ -72,6 +72,12 @@ Optional properties:
+ - prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
+   <1> (forcibly enable), property absent (retain settings set by
+   firmware)
++- arm,shared-override : The default behavior of the pl310 cache controller with
++  respect to the shareable attribute is to transform "normal memory
++  non-cacheable transactions" into "cacheable no allocate" (for reads) or
++  "write through no write allocate" (for writes).
++  On systems where this may cause DMA buffer corruption, this property must be
++  specified to indicate that such transforms are precluded.
+ 
+ Example:
+ 
+--- a/arch/arm/mm/cache-l2x0.c
++++ b/arch/arm/mm/cache-l2x0.c
+@@ -1171,6 +1171,11 @@ static void __init l2c310_of_parse(const
+ 		}
+ 	}
+ 
++	if (of_property_read_bool(np, "arm,shared-override")) {
++		*aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
++		*aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
++	}
++
+ 	prefetch = l2x0_saved_regs.prefetch_ctrl;
+ 
+ 	ret = of_property_read_u32(np, "arm,double-linefill", &val);

target/linux/bcm53xx/patches-4.1/079-ARM-BCM5301X-activate-some-additional-options-in-pl3.patch

@@ -0,0 +1,29 @@
+From e8ec653c767f56346eb1fadbc07e0706d6dbd56f Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <[email protected]>
+Date: Thu, 14 May 2015 00:38:28 +0200
+Subject: [PATCH 3/3] ARM: BCM5301X: activate some additional options in pl310
+ cache controller
+
+In the default Broadcom SDK the shared override is activated for this
+cache controller, do the same in the upstream code. Data and
+instruction prefetching is not activated by default for this cache
+controller on the bcm53xx SoC, do it manually like it is done in the
+vendor SDK.
+
+Signed-off-by: Hauke Mehrtens <[email protected]>
+---
+ arch/arm/boot/dts/bcm5301x.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -78,6 +78,9 @@
+ 			compatible = "arm,pl310-cache";
+ 			reg = <0x2000 0x1000>;
+ 			cache-unified;
++			arm,shared-override;
++			prefetch-data = <1>;
++			prefetch-instr = <1>;
+ 			cache-level = <2>;
+ 		};
+ 	};

target/linux/bcm53xx/patches-4.1/305-ARM-BCM53XX-set-customized-AUXCTL.patch

@@ -1,30 +0,0 @@
-From 4a658590f83c1e916ab63ed7fe6f0841924247db Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <[email protected]>
-Date: Fri, 3 Oct 2014 18:37:33 +0200
-Subject: [PATCH 2/2] ARM: BCM53XX: set customized AUXCTL
-
-This activated some more features in the l310 cache.
-
-This is based on some vendor code
-
-Signed-off-by: Hauke Mehrtens <[email protected]>
----
- arch/arm/mach-bcm/bcm_5301x.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/arch/arm/mach-bcm/bcm_5301x.c
-+++ b/arch/arm/mach-bcm/bcm_5301x.c
-@@ -50,7 +50,12 @@ static const char __initconst *bcm5301x_
- };
- 
- DT_MACHINE_START(BCM5301X, "BCM5301X")
--	.l2c_aux_val	= 0,
-+	.l2c_aux_val	= L310_AUX_CTRL_CACHE_REPLACE_RR |
-+			  L310_AUX_CTRL_DATA_PREFETCH |
-+			  L310_AUX_CTRL_INSTR_PREFETCH |
-+			  L310_AUX_CTRL_EARLY_BRESP |
-+			  L2C_AUX_CTRL_SHARED_OVERRIDE |
-+			  L310_AUX_CTRL_FULL_LINE_ZERO,
- 	.l2c_aux_mask	= ~0,
- 	.init_early	= bcm5301x_init_early,
- 	.dt_compat	= bcm5301x_dt_compat,

target/linux/bcm53xx/patches-4.1/340-ARM-BCM5301X-Add-profiling-support.patch

@@ -4,7 +4,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
 ---
 --- a/arch/arm/boot/dts/bcm5301x.dtsi
 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
-@@ -82,6 +82,13 @@
+@@ -85,6 +85,13 @@
  		};
  	};