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@@ -1,3 +1,53 @@
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+commit fdf9a4517b60d847b9bc0a30249efd96559fa450
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+Author: Felix Fietkau <[email protected]>
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+Date: Tue Sep 9 09:48:30 2014 +0200
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+
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+ ath9k_hw: fix PLL clock initialization for newer SoC
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+
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+ On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL
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+ register changed. This currently breaks at least 5/10 MHz operation.
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+ AR933x uses the old layout.
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+
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+ It might also have been causing other stability issues because of the
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+ different location of the PLL_BYPASS bit which needs to be set during
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+ PLL clock initialization.
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+
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+ This patch also removes more instances of hardcoded register values in
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+ favor of properly computed ones with the PLL_BYPASS bit added.
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+
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+ Reported-by: Lorenzo Bianconi <[email protected]>
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+ Signed-off-by: Felix Fietkau <[email protected]>
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+
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+commit b6d1f51cd8bdc9d952147a960fbf1f261d8e4188
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+Author: Felix Fietkau <[email protected]>
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+Date: Mon Sep 8 18:35:08 2014 +0200
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+
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+ ath9k_hw: reduce ANI spur immunity setting on HT40 extension channel
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+
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+ The cycpwr_thr1 value needs to be lower on the extension channel than on
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+ the control channel, similar to how the register settings are programmed
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+ in the initvals.
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+
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+ Also drop the unnecessary check for HT40 - this register can always be
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+ written. This patch has been reported to improve HT40 stability and
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+ throughput in some environments.
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+
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+ Signed-off-by: Felix Fietkau <[email protected]>
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+
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+commit 5ad2dfbaa19aa45d29184d30c8c5dae0e110074a
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+Author: Felix Fietkau <[email protected]>
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+Date: Mon Sep 8 18:31:26 2014 +0200
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+
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+ Revert "ath9k_hw: reduce ANI firstep range for older chips"
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+
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+ This reverts commit 09efc56345be4146ab9fc87a55c837ed5d6ea1ab
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+
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+ I've received reports that this change is decreasing throughput in some
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+ rare conditions on an AR9280 based device
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+
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+ Cc: [email protected]
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+ Signed-off-by: Felix Fietkau <[email protected]>
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+
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commit 4c82fc569cf2f29e6c66d98ef4a1b0f3b6a98e9d
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Author: Felix Fietkau <[email protected]>
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Date: Sat Sep 27 22:39:27 2014 +0200
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@@ -476,7 +526,44 @@ Date: Sat Sep 27 15:57:09 2014 +0200
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return;
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}
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-@@ -1192,9 +1189,12 @@ static void ath9k_hw_set_operating_mode(
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+@@ -704,6 +701,8 @@ static void ath9k_hw_init_pll(struct ath
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+ {
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+ u32 pll;
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+
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++ pll = ath9k_hw_compute_pll_control(ah, chan);
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++
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+ if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
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+ /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
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+ REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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+@@ -754,7 +753,8 @@ static void ath9k_hw_init_pll(struct ath
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+ REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
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+ AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
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+
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+- REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
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++ REG_WRITE(ah, AR_RTC_PLL_CONTROL,
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++ pll | AR_RTC_9300_PLL_BYPASS);
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+ udelay(1000);
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+
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+ /* program refdiv, nint, frac to RTC register */
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+@@ -770,7 +770,8 @@ static void ath9k_hw_init_pll(struct ath
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+ } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
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+ u32 regval, pll2_divint, pll2_divfrac, refdiv;
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+
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+- REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
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++ REG_WRITE(ah, AR_RTC_PLL_CONTROL,
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++ pll | AR_RTC_9300_SOC_PLL_BYPASS);
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+ udelay(1000);
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+
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+ REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
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+@@ -843,7 +844,6 @@ static void ath9k_hw_init_pll(struct ath
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+ udelay(1000);
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+ }
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+
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+- pll = ath9k_hw_compute_pll_control(ah, chan);
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+ if (AR_SREV_9565(ah))
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+ pll |= 0x40000;
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+ REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
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+@@ -1192,9 +1192,12 @@ static void ath9k_hw_set_operating_mode(
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switch (opmode) {
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case NL80211_IFTYPE_ADHOC:
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@@ -505,3 +592,94 @@ Date: Sat Sep 27 15:57:09 2014 +0200
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#define AR_SREV_9340_13_OR_LATER(_ah) \
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(AR_SREV_9340((_ah)) && \
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((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
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+@@ -1240,12 +1244,23 @@ enum {
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+ #define AR_CH0_DPLL3_PHASE_SHIFT_S 23
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+ #define AR_PHY_CCA_NOM_VAL_2GHZ -118
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+
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++#define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f
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++#define AR_RTC_9300_SOC_PLL_DIV_INT_S 0
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++#define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc0
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++#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 6
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++#define AR_RTC_9300_SOC_PLL_REFDIV 0x01f00000
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++#define AR_RTC_9300_SOC_PLL_REFDIV_S 20
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++#define AR_RTC_9300_SOC_PLL_CLKSEL 0x06000000
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++#define AR_RTC_9300_SOC_PLL_CLKSEL_S 25
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++#define AR_RTC_9300_SOC_PLL_BYPASS 0x08000000
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++
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+ #define AR_RTC_9300_PLL_DIV 0x000003ff
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+ #define AR_RTC_9300_PLL_DIV_S 0
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+ #define AR_RTC_9300_PLL_REFDIV 0x00003C00
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+ #define AR_RTC_9300_PLL_REFDIV_S 10
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+ #define AR_RTC_9300_PLL_CLKSEL 0x0000C000
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+ #define AR_RTC_9300_PLL_CLKSEL_S 14
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++#define AR_RTC_9300_PLL_BYPASS 0x00010000
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+
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+ #define AR_RTC_9160_PLL_DIV 0x000003ff
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+ #define AR_RTC_9160_PLL_DIV_S 0
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+--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
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++++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
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+@@ -1004,9 +1004,11 @@ static bool ar5008_hw_ani_control_new(st
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+ case ATH9K_ANI_FIRSTEP_LEVEL:{
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+ u32 level = param;
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+
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+- value = level;
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++ value = level * 2;
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+ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
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+ AR_PHY_FIND_SIG_FIRSTEP, value);
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++ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
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++ AR_PHY_FIND_SIG_FIRSTEP_LOW, value);
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+
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+ if (level != aniState->firstepLevel) {
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+ ath_dbg(common, ANI,
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+@@ -1040,9 +1042,8 @@ static bool ar5008_hw_ani_control_new(st
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+ REG_RMW_FIELD(ah, AR_PHY_TIMING5,
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+ AR_PHY_TIMING5_CYCPWR_THR1, value);
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+
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+- if (IS_CHAN_HT40(ah->curchan))
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+- REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
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+- AR_PHY_EXT_TIMING5_CYCPWR_THR1, value);
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++ REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
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++ AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1);
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+
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+ if (level != aniState->spurImmunityLevel) {
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+ ath_dbg(common, ANI,
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+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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+@@ -517,6 +517,23 @@ static void ar9003_hw_spur_mitigate(stru
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+ ar9003_hw_spur_mitigate_ofdm(ah, chan);
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+ }
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+
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++static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
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++ struct ath9k_channel *chan)
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++{
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++ u32 pll;
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++
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++ pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
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++
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++ if (chan && IS_CHAN_HALF_RATE(chan))
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++ pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
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++ else if (chan && IS_CHAN_QUARTER_RATE(chan))
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++ pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
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++
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++ pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
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++
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++ return pll;
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++}
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++
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+ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
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+ struct ath9k_channel *chan)
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+ {
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+@@ -1781,7 +1798,12 @@ void ar9003_hw_attach_phy_ops(struct ath
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+
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+ priv_ops->rf_set_freq = ar9003_hw_set_channel;
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+ priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
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+- priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
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++
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++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
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++ priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
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++ else
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++ priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
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++
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+ priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
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+ priv_ops->init_bb = ar9003_hw_init_bb;
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+ priv_ops->process_ini = ar9003_hw_process_ini;
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Felix Fietkau