generic: 5.15: move mvebu aardvark patch from pending to backport

Move mvebu aardvark patch from pending to backport as they got merged
upstream.
One additional patch is needed as a later fixup for it.

Signed-off-by: Christian Marangi <[email protected]>

target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch → target/linux/generic/backport-5.15/344-v5.18-01-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch

@@ -1,8 +1,8 @@
-From a719f7ba7fcba05d85801c6f0267f389a21627c1 Mon Sep 17 00:00:00 2001
+From 4bf18d5a2dd02db8c5b16a2cfae513510506df5b Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
-Date: Fri, 24 Sep 2021 13:03:02 +0200
-Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver
- configuration
+Date: Thu, 3 Feb 2022 22:44:40 +0100
+Subject: [PATCH 1/2] phy: marvell: phy-mvebu-a3700-comphy: Remove port from
+ driver configuration
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
@@ -25,6 +25,8 @@ driver code which parses it. This also simplifies the driver.
 Signed-off-by: Pali Rohár <[email protected]>
 Signed-off-by: Marek Behún <[email protected]>
 Reviewed-by: Miquel Raynal <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
 ---
  drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 62 +++++++++-----------
  1 file changed, 29 insertions(+), 33 deletions(-)

target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch → target/linux/generic/backport-5.15/344-v5.18-02-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch

@@ -1,7 +1,7 @@
-From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001
+From 934337080c6c59b75db76b180b509f218640ad48 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
-Date: Thu, 23 Sep 2021 19:20:13 +0200
-Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel
+Date: Thu, 3 Feb 2022 22:44:41 +0100
+Subject: [PATCH 2/2] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel
  implementation
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
@@ -46,16 +46,19 @@ original code not conforming to kernel standards. Also PCIe mode poweroff
 support was added here, and PHY reset support. These changes are also going
 to be sent to ARM Trusted Firmware.
 
-Signed-off-by: Pali Rohár <[email protected]>
-Acked-by: Miquel Raynal <[email protected]>
 [ Pali did the porting from ATF.
   I (Marek) then fixed some register names, some various other things,
   added some comments and refactored the code to kernel standards. Also
   fixed PHY poweroff and added PHY reset. ]
+
+Signed-off-by: Pali Rohár <[email protected]>
+Acked-by: Miquel Raynal <[email protected]>
 Signed-off-by: Marek Behún <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
 ---
- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++--
- 1 file changed, 1234 insertions(+), 117 deletions(-)
+ drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1332 ++++++++++++++++--
+ 1 file changed, 1215 insertions(+), 117 deletions(-)
 
 --- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
 +++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
@@ -78,7 +81,7 @@ Signed-off-by: Marek Behún <[email protected]>
  #include <linux/io.h>
  #include <linux/iopoll.h>
  #include <linux/mfd/syscon.h>
-@@ -18,103 +22,1147 @@
+@@ -18,103 +22,1118 @@
  #include <linux/phy.h>
  #include <linux/phy/phy.h>
  #include <linux/platform_device.h>
@@ -480,23 +483,23 @@ Signed-off-by: Marek Behún <[email protected]>
 -	struct arm_smccc_res res;
 -	s32 ret;
 +	u32 val;
- 
--	arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
--	ret = res.a0;
++
 +	val = readl(addr);
 +	val = (val & ~mask) | (data & mask);
 +	writel(val, addr);
 +}
  
+-	arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
+-	ret = res.a0;
++static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
++{
++	u16 val;
+ 
 -	switch (ret) {
 -	case SMCCC_RET_SUCCESS:
 -		return 0;
 -	case SMCCC_RET_NOT_SUPPORTED:
 -		return -EOPNOTSUPP;
-+static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
-+{
-+	u16 val;
-+
 +	val = readw(addr);
 +	val = (val & ~mask) | (data & mask);
 +	writew(val, addr);
@@ -708,12 +711,10 @@ Signed-off-by: Marek Behún <[email protected]>
 +	ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN,
 +				   PLL_READY_TX_BIT, COMPHY_PLL_SLEEP,
 +				   COMPHY_PLL_TIMEOUT);
-+	if (ret) {
++	if (ret)
 +		dev_err(lane->dev, "Failed to lock SATA PLL\n");
-+		return ret;
-+	}
 +
-+	return 0;
++	return ret;
 +}
 +
 +static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,
@@ -827,7 +828,8 @@ Signed-off-by: Marek Behún <[email protected]>
 +	mask = REF_FREF_SEL_MASK;
 +	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
 +
-+	/* 10. Program COMPHY register PHY_GEN_MAX[1:0]
++	/*
++	 * 10. Program COMPHY register PHY_GEN_MAX[1:0]
 +	 * This step is mentioned in the flow received from verification team.
 +	 * However the PHY_GEN_MAX value is only meaningful for other interfaces
 +	 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or
@@ -846,9 +848,8 @@ Signed-off-by: Marek Behún <[email protected]>
 +	 * 12. As long as DFE function needs to be enabled in any mode,
 +	 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
 +	 * for real chip during COMPHY power on.
-+	 * The step 14 exists (and empty) in the original initialization flow
-+	 * obtained from the verification team. According to the functional
-+	 * specification DFE_UPDATE_EN already has the default value 0x3F
++	 * The value of the DFE_UPDATE_EN already is 0x3F, because it is the
++	 * default value after reset of the PHY.
 +	 */
 +
 +	/*
@@ -867,19 +868,7 @@ Signed-off-by: Marek Behún <[email protected]>
 +				    lane->submode != PHY_INTERFACE_MODE_2500BASEX);
 +
 +	/*
-+	 * 14. [Simulation Only] should not be used for real chip.
-+	 * By pass power up calibration by programming EXT_FORCE_CAL_DONE
-+	 * (R02h[9]) to 1 to shorten COMPHY simulation time.
-+	 */
-+
-+	/*
-+	 * 15. [Simulation Only: should not be used for real chip]
-+	 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training
-+	 * simulation time.
-+	 */
-+
-+	/*
-+	 * 16. Check the PHY Polarity invert bit
++	 * 14. Check the PHY Polarity invert bit
 +	 */
 +	data = 0x0;
 +	if (lane->invert_tx)
@@ -890,7 +879,7 @@ Signed-off-by: Marek Behún <[email protected]>
 +	comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
 +
 +	/*
-+	 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
++	 * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
 +	 * start PHY power up sequence. All the PHY register programming should
 +	 * be done before PIN_PU_PLL=1. There should be no register programming
 +	 * for normal PHY operation from this point.
@@ -900,7 +889,7 @@ Signed-off-by: Marek Behún <[email protected]>
 +	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
 +
 +	/*
-+	 * 18. Wait for PHY power up sequence to finish by checking output ports
++	 * 16. Wait for PHY power up sequence to finish by checking output ports
 +	 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
 +	 */
 +	ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
@@ -914,12 +903,12 @@ Signed-off-by: Marek Behún <[email protected]>
 +	}
 +
 +	/*
-+	 * 19. Set COMPHY input port PIN_TX_IDLE=0
++	 * 17. Set COMPHY input port PIN_TX_IDLE=0
 +	 */
 +	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);
 +
 +	/*
-+	 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
++	 * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
 +	 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the
 +	 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to
 +	 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please
@@ -941,13 +930,11 @@ Signed-off-by: Marek Behún <[email protected]>
 +	ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
 +				     PHY_RX_INIT_DONE_BIT,
 +				     COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
-+	if (ret) {
++	if (ret)
 +		dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n",
 +			lane->id);
-+		return ret;
-+	}
 +
-+	return 0;
++	return ret;
  }
  
 -static int mvebu_a3700_comphy_get_fw_mode(int lane,
@@ -1107,12 +1094,10 @@ Signed-off-by: Marek Behún <[email protected]>
 +
 +	ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
 +				   COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
-+	if (ret) {
++	if (ret)
 +		dev_err(lane->dev, "Failed to lock USB3 PLL\n");
-+		return ret;
-+	}
 +
-+	return 0;
++	return ret;
 +}
 +
 +static int
@@ -1197,21 +1182,10 @@ Signed-off-by: Marek Behún <[email protected]>
 +
 +	ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
 +				   COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
-+	if (ret) {
++	if (ret)
 +		dev_err(lane->dev, "Failed to lock PCIE PLL\n");
-+		return ret;
-+	}
 +
-+	return 0;
-+}
-+
-+static void
-+mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)
-+{
-+	/*
-+	 * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not
-+	 * need to power off USB3 PHY again.
-+	 */
++	return ret;
 +}
 +
 +static void
@@ -1285,7 +1259,7 @@ Signed-off-by: Marek Behún <[email protected]>
  					  enum phy_mode mode,
  					  int submode)
  {
-@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod
+@@ -122,7 +1141,7 @@ static int mvebu_a3700_comphy_get_fw_mod
  
  	/* Unused PHY mux value is 0x0 */
  	if (mode == PHY_MODE_INVALID)
@@ -1294,7 +1268,7 @@ Signed-off-by: Marek Behún <[email protected]>
  
  	for (i = 0; i < n; i++) {
  		if (mvebu_a3700_comphy_modes[i].lane == lane &&
-@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod
+@@ -132,27 +1151,30 @@ static int mvebu_a3700_comphy_get_fw_mod
  	}
  
  	if (i == n)
@@ -1310,10 +1284,10 @@ Signed-off-by: Marek Behún <[email protected]>
  {
  	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
 -	int fw_mode;
--
+ 
 -	if (submode == PHY_INTERFACE_MODE_1000BASEX)
 -		submode = PHY_INTERFACE_MODE_SGMII;
- 
+-
 -	fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode,
 -						 submode);
 -	if (fw_mode < 0) {
@@ -1335,7 +1309,7 @@ Signed-off-by: Marek Behún <[email protected]>
  	/* Just remember the mode, ->power_on() will do the real setup */
  	lane->mode = mode;
  	lane->submode = submode;
-@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s
+@@ -163,76 +1185,77 @@ static int mvebu_a3700_comphy_set_mode(s
  static int mvebu_a3700_comphy_power_on(struct phy *phy)
  {
  	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
@@ -1423,21 +1397,30 @@ Signed-off-by: Marek Behún <[email protected]>
 -	return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
 +	switch (lane->mode) {
 +	case PHY_MODE_USB_HOST_SS:
-+		mvebu_a3700_comphy_usb3_power_off(lane);
-+		return 0;
++		/*
++		 * The USB3 MAC sets the USB3 PHY to low state, so we do not
++		 * need to power off USB3 PHY again.
++		 */
++		break;
++
 +	case PHY_MODE_SATA:
 +		mvebu_a3700_comphy_sata_power_off(lane);
-+		return 0;
++		break;
++
 +	case PHY_MODE_ETHERNET:
 +		mvebu_a3700_comphy_ethernet_power_off(lane);
-+		return 0;
++		break;
++
 +	case PHY_MODE_PCIE:
 +		mvebu_a3700_comphy_pcie_power_off(lane);
-+		return 0;
++		break;
++
 +	default:
 +		dev_err(lane->dev, "invalid COMPHY mode\n");
 +		return -EINVAL;
 +	}
++
++	return 0;
  }
  
  static const struct phy_ops mvebu_a3700_comphy_ops = {
@@ -1447,7 +1430,7 @@ Signed-off-by: Marek Behún <[email protected]>
  	.set_mode	= mvebu_a3700_comphy_set_mode,
  	.owner		= THIS_MODULE,
  };
-@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl
+@@ -256,13 +1279,75 @@ static struct phy *mvebu_a3700_comphy_xl
  		return ERR_PTR(-EINVAL);
  	}
  
@@ -1523,7 +1506,7 @@ Signed-off-by: Marek Behún <[email protected]>
  
  	for_each_available_child_of_node(pdev->dev.of_node, child) {
  		struct mvebu_a3700_comphy_lane *lane;
-@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru
+@@ -277,7 +1362,7 @@ static int mvebu_a3700_comphy_probe(stru
  			continue;
  		}
  
@@ -1532,7 +1515,7 @@ Signed-off-by: Marek Behún <[email protected]>
  			dev_err(&pdev->dev, "invalid 'reg' property\n");
  			continue;
  		}
-@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru
+@@ -295,15 +1380,26 @@ static int mvebu_a3700_comphy_probe(stru
  			return PTR_ERR(phy);
  		}
  
@@ -1554,7 +1537,12 @@ Signed-off-by: Marek Behún <[email protected]>
  	}
  
  	provider = devm_of_phy_provider_register(&pdev->dev,
-@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370
+ 						 mvebu_a3700_comphy_xlate);
++
+ 	return PTR_ERR_OR_ZERO(provider);
+ }
+ 
+@@ -323,5 +1419,7 @@ static struct platform_driver mvebu_a370
  module_platform_driver(mvebu_a3700_comphy_driver);
  
  MODULE_AUTHOR("Miquèl Raynal <[email protected]>");

target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch → target/linux/generic/backport-5.15/345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch

@@ -1,8 +1,8 @@
-From 66c51c39fd4bf05e99debf0e71de5704231c57dc Mon Sep 17 00:00:00 2001
+From 73a78b6130d9e13daca22b86ad52f063b9403e03 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
-Date: Thu, 23 Sep 2021 19:26:26 +0200
-Subject: [PATCH] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy
- node
+Date: Wed, 8 Dec 2021 03:40:35 +0100
+Subject: [PATCH 1/1] arm64: dts: marvell: armada-37xx: Add xtal clock to
+ comphy node
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
@@ -14,6 +14,7 @@ xtal rate (which, as far as we know, is used by all the existing boards).
 
 Signed-off-by: Pali Rohár <[email protected]>
 Signed-off-by: Marek Behún <[email protected]>
+Signed-off-by: Gregory CLEMENT <[email protected]>
 ---
  arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++
  1 file changed, 2 insertions(+)

target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch → target/linux/generic/backport-5.15/346-v5.18-01-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch

@@ -1,8 +1,8 @@
-From 750bb44dbbe9dfb4ba3e1f8a746b831b39ba3cd9 Mon Sep 17 00:00:00 2001
+From ee995101fde67f85a3cd4c74f4f92fc4592e726b Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
-Date: Thu, 23 Sep 2021 19:35:57 +0200
-Subject: [PATCH] Revert "ata: ahci: mvebu: Make SATA PHY optional for Armada
- 3720"
+Date: Thu, 3 Feb 2022 22:44:42 +0100
+Subject: [PATCH 1/3] Revert "ata: ahci: mvebu: Make SATA PHY optional for
+ Armada 3720"
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
@@ -20,6 +20,9 @@ remove this flag completely.
 Signed-off-by: Pali Rohár <[email protected]>
 Signed-off-by: Marek Behún <[email protected]>
 Acked-by: Miquel Raynal <[email protected]>
+Acked-by: Damien Le Moal <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
 ---
  drivers/ata/ahci.h             | 2 --
  drivers/ata/ahci_mvebu.c       | 2 +-

target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch → target/linux/generic/backport-5.15/346-v5.18-02-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch

@@ -1,8 +1,8 @@
-From 9f0dfb279b1dd505d5e10b10e4a78a62030978d8 Mon Sep 17 00:00:00 2001
+From 8e10548f7f4814e530857d2049d6af6bc78add53 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
-Date: Thu, 23 Sep 2021 19:40:06 +0200
-Subject: [PATCH] Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional for
- Armada 3720"
+Date: Thu, 3 Feb 2022 22:44:43 +0100
+Subject: [PATCH 2/3] Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional
+ for Armada 3720"
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
@@ -22,6 +22,9 @@ remove this callback completely.
 Signed-off-by: Pali Rohár <[email protected]>
 Signed-off-by: Marek Behún <[email protected]>
 Acked-by: Miquel Raynal <[email protected]>
+Acked-by: Greg Kroah-Hartman <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
 ---
  drivers/usb/host/xhci-mvebu.c | 42 -----------------------------------
  drivers/usb/host/xhci-mvebu.h |  6 -----

target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch → target/linux/generic/backport-5.15/346-v5.18-03-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch

@@ -1,8 +1,8 @@
-From 9a352062b7e3857742389dff6f64393481dc755e Mon Sep 17 00:00:00 2001
+From 9a4556dad7bd0a6b8339cb72e169f5c76f2af6f1 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
-Date: Thu, 23 Sep 2021 19:37:05 +0200
-Subject: [PATCH] Revert "PCI: aardvark: Fix initialization with old Marvell's
- Arm Trusted Firmware"
+Date: Thu, 3 Feb 2022 22:44:44 +0100
+Subject: [PATCH 3/3] Revert "PCI: aardvark: Fix initialization with old
+ Marvell's Arm Trusted Firmware"
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
@@ -17,13 +17,16 @@ So remove dead code which handles -EOPNOTSUPP return value.
 Signed-off-by: Pali Rohár <[email protected]>
 Signed-off-by: Marek Behún <[email protected]>
 Acked-by: Miquel Raynal <[email protected]>
+Acked-by: Lorenzo Pieralisi <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
 ---
  drivers/pci/controller/pci-aardvark.c | 4 +---
  1 file changed, 1 insertion(+), 3 deletions(-)
 
 --- a/drivers/pci/controller/pci-aardvark.c
 +++ b/drivers/pci/controller/pci-aardvark.c
-@@ -1631,9 +1631,7 @@ static int advk_pcie_enable_phy(struct a
+@@ -1642,9 +1642,7 @@ static int advk_pcie_enable_phy(struct a
  	}
  
  	ret = phy_power_on(pcie->phy);

target/linux/generic/backport-5.15/347-v6.0-phy-marvell-phy-mvebu-a3700-comphy-Remove-broken-res.patch

@@ -0,0 +1,194 @@
+From 0a6fc70d76bddf98278af2ac000379c82aec8f11 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
+Date: Mon, 29 Aug 2022 10:30:46 +0200
+Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset
+ support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reset support for SATA PHY is somehow broken and after calling it, kernel
+is not able to detect and initialize SATA disk Samsung SSD 850 EMT0 [1].
+
+Reset support was introduced in commit 934337080c6c ("phy: marvell:
+phy-mvebu-a3700-comphy: Add native kernel implementation") as part of
+complete rewrite of this driver. v1 patch series of that commit [2] did
+not contain reset support and was tested that is working fine with
+Ethernet, SATA and USB PHYs without issues too.
+
+So for now remove broken reset support and change implementation of
+power_off callback to power off all functions on specified lane (and not
+only selected function) because during startup kernel does not know which
+function was selected and configured by bootloader. Same logic was used
+also in v1 patch series of that commit.
+
+This change fixes issues with initialization of SATA disk Samsung SSD 850
+and disk is working again, like before mentioned commit.
+
+Once problem with PHY reset callback is solved its functionality could be
+re-introduced. But for now it is unknown why it does not work.
+
+[1] - https://lore.kernel.org/r/20220531124159.3e4lgn2v462irbtz@shindev/
+[2] - https://lore.kernel.org/r/[email protected]/
+
+Reported-by: Shinichiro Kawasaki <[email protected]>
+Fixes: 934337080c6c ("phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation")
+Cc: [email protected] # v5.18+
+Signed-off-by: Pali Rohár <[email protected]>
+Tested-by: Shinichiro Kawasaki <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Vinod Koul <[email protected]>
+---
+ drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 87 ++++----------------
+ 1 file changed, 17 insertions(+), 70 deletions(-)
+
+--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+@@ -274,7 +274,6 @@ struct mvebu_a3700_comphy_lane {
+ 	int submode;
+ 	bool invert_tx;
+ 	bool invert_rx;
+-	bool needs_reset;
+ };
+ 
+ struct gbe_phy_init_data_fix {
+@@ -1097,40 +1096,12 @@ mvebu_a3700_comphy_pcie_power_off(struct
+ 			    0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
+ }
+ 
+-static int mvebu_a3700_comphy_reset(struct phy *phy)
++static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)
+ {
+-	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
+-	u16 mask, data;
+-
+-	dev_dbg(lane->dev, "resetting lane %d\n", lane->id);
+-
+-	/* COMPHY reset for internal logic */
+-	comphy_lane_reg_set(lane, COMPHY_SFT_RESET,
+-			    SFT_RST_NO_REG, SFT_RST_NO_REG);
+-
+-	/* COMPHY register reset (cleared automatically) */
+-	comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
+-
+-	/* PIPE soft and register reset */
+-	data = PIPE_SOFT_RESET | PIPE_REG_RESET;
+-	mask = data;
+-	comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
+-
+-	/* Release PIPE register reset */
+-	comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL,
+-			    0x0, PIPE_REG_RESET);
+-
+-	/* Reset SB configuration register (only for lanes 0 and 1) */
+-	if (lane->id == 0 || lane->id == 1) {
+-		u32 mask, data;
+-
+-		data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT |
+-		       PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;
+-		mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT;
+-		comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
+-	}
+-
+-	return 0;
++	/*
++	 * The USB3 MAC sets the USB3 PHY to low state, so we do not
++	 * need to power off USB3 PHY again.
++	 */
+ }
+ 
+ static bool mvebu_a3700_comphy_check_mode(int lane,
+@@ -1171,10 +1142,6 @@ static int mvebu_a3700_comphy_set_mode(s
+ 	    (lane->mode != mode || lane->submode != submode))
+ 		return -EBUSY;
+ 
+-	/* If changing mode, ensure reset is called */
+-	if (lane->mode != PHY_MODE_INVALID && lane->mode != mode)
+-		lane->needs_reset = true;
+-
+ 	/* Just remember the mode, ->power_on() will do the real setup */
+ 	lane->mode = mode;
+ 	lane->submode = submode;
+@@ -1185,7 +1152,6 @@ static int mvebu_a3700_comphy_set_mode(s
+ static int mvebu_a3700_comphy_power_on(struct phy *phy)
+ {
+ 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
+-	int ret;
+ 
+ 	if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,
+ 					   lane->submode)) {
+@@ -1193,14 +1159,6 @@ static int mvebu_a3700_comphy_power_on(s
+ 		return -EINVAL;
+ 	}
+ 
+-	if (lane->needs_reset) {
+-		ret = mvebu_a3700_comphy_reset(phy);
+-		if (ret)
+-			return ret;
+-
+-		lane->needs_reset = false;
+-	}
+-
+ 	switch (lane->mode) {
+ 	case PHY_MODE_USB_HOST_SS:
+ 		dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
+@@ -1224,38 +1182,28 @@ static int mvebu_a3700_comphy_power_off(
+ {
+ 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
+ 
+-	switch (lane->mode) {
+-	case PHY_MODE_USB_HOST_SS:
+-		/*
+-		 * The USB3 MAC sets the USB3 PHY to low state, so we do not
+-		 * need to power off USB3 PHY again.
+-		 */
+-		break;
+-
+-	case PHY_MODE_SATA:
+-		mvebu_a3700_comphy_sata_power_off(lane);
+-		break;
+-
+-	case PHY_MODE_ETHERNET:
++	switch (lane->id) {
++	case 0:
++		mvebu_a3700_comphy_usb3_power_off(lane);
+ 		mvebu_a3700_comphy_ethernet_power_off(lane);
+-		break;
+-
+-	case PHY_MODE_PCIE:
++		return 0;
++	case 1:
+ 		mvebu_a3700_comphy_pcie_power_off(lane);
+-		break;
+-
++		mvebu_a3700_comphy_ethernet_power_off(lane);
++		return 0;
++	case 2:
++		mvebu_a3700_comphy_usb3_power_off(lane);
++		mvebu_a3700_comphy_sata_power_off(lane);
++		return 0;
+ 	default:
+ 		dev_err(lane->dev, "invalid COMPHY mode\n");
+ 		return -EINVAL;
+ 	}
+-
+-	return 0;
+ }
+ 
+ static const struct phy_ops mvebu_a3700_comphy_ops = {
+ 	.power_on	= mvebu_a3700_comphy_power_on,
+ 	.power_off	= mvebu_a3700_comphy_power_off,
+-	.reset		= mvebu_a3700_comphy_reset,
+ 	.set_mode	= mvebu_a3700_comphy_set_mode,
+ 	.owner		= THIS_MODULE,
+ };
+@@ -1393,8 +1341,7 @@ static int mvebu_a3700_comphy_probe(stru
+ 		 * To avoid relying on the bootloader/firmware configuration,
+ 		 * power off all comphys.
+ 		 */
+-		mvebu_a3700_comphy_reset(phy);
+-		lane->needs_reset = false;
++		mvebu_a3700_comphy_power_off(phy);
+ 	}
+ 
+ 	provider = devm_of_phy_provider_register(&pdev->dev,