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+/*
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+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips
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+ * Copyright (c) 2009 Gabor Juhos <[email protected]>
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+ *
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+ * This driver was base on: net/dsa/mv88e6060.c
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+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips
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+ * Copyright (c) 2008-2009 Marvell Semiconductor
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#include <linux/list.h>
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+#include <linux/netdevice.h>
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+#include <linux/phy.h>
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+#include "dsa_priv.h"
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+
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+#define REG_BASE 0x10
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+#define REG_PHY(p) (REG_BASE + (p))
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+#define REG_PORT(p) (REG_BASE + 8 + (p))
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+#define REG_GLOBAL (REG_BASE + 0x0f)
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+#define NUM_PORTS 7
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+
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+static int reg_read(struct dsa_switch *ds, int addr, int reg)
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+{
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+ return mdiobus_read(ds->master_mii_bus, addr, reg);
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+}
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+
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+#define REG_READ(addr, reg) \
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+ ({ \
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+ int __ret; \
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+ \
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+ __ret = reg_read(ds, addr, reg); \
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+ if (__ret < 0) \
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+ return __ret; \
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+ __ret; \
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+ })
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+
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+
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+static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
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+{
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+ return mdiobus_write(ds->master_mii_bus, addr, reg, val);
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+}
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+
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+#define REG_WRITE(addr, reg, val) \
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+ ({ \
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+ int __ret; \
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+ \
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+ __ret = reg_write(ds, addr, reg, val); \
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+ if (__ret < 0) \
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+ return __ret; \
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+ })
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+
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+static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr)
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+{
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+ int ret;
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+
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+ ret = mdiobus_read(bus, REG_PORT(0), 0x03);
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+ if (ret >= 0) {
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+ ret &= 0xfff0;
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+ if (ret == 0x1530)
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+ return "Marvell 88E6063";
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+ }
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+
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+ return NULL;
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+}
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+
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+static int mv88e6063_switch_reset(struct dsa_switch *ds)
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+{
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+ int i;
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+ int ret;
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+
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+ /*
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+ * Set all ports to the disabled state.
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+ */
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+ for (i = 0; i < NUM_PORTS; i++) {
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+ ret = REG_READ(REG_PORT(i), 0x04);
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+ REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
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+ }
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+
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+ /*
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+ * Wait for transmit queues to drain.
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+ */
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+ msleep(2);
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+
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+ /*
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+ * Reset the switch.
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+ */
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+ REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
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+
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+ /*
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+ * Wait up to one second for reset to complete.
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+ */
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+ for (i = 0; i < 1000; i++) {
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+ ret = REG_READ(REG_GLOBAL, 0x00);
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+ if ((ret & 0x8000) == 0x0000)
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+ break;
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+
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+ msleep(1);
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+ }
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+ if (i == 1000)
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+ return -ETIMEDOUT;
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+
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+ return 0;
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+}
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+
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+static int mv88e6063_setup_global(struct dsa_switch *ds)
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+{
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+ /*
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+ * Disable discarding of frames with excessive collisions,
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+ * set the maximum frame size to 1536 bytes, and mask all
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+ * interrupt sources.
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+ */
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+ REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
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+
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+ /*
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+ * Enable automatic address learning, set the address
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+ * database size to 1024 entries, and set the default aging
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+ * time to 5 minutes.
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+ */
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+ REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
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+
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+ return 0;
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+}
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+
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+static int mv88e6063_setup_port(struct dsa_switch *ds, int p)
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+{
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+ int addr = REG_PORT(p);
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+
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+ /*
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+ * Do not force flow control, disable Ingress and Egress
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+ * Header tagging, disable VLAN tunneling, and set the port
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+ * state to Forwarding. Additionally, if this is the CPU
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+ * port, enable Ingress and Egress Trailer tagging mode.
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+ */
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+ REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
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+
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+ /*
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+ * Port based VLAN map: give each port its own address
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+ * database, allow the CPU port to talk to each of the 'real'
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+ * ports, and allow each of the 'real' ports to only talk to
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+ * the CPU port.
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+ */
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+ REG_WRITE(addr, 0x06,
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+ ((p & 0xf) << 12) |
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+ (dsa_is_cpu_port(ds, p) ?
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+ ds->phys_port_mask :
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+ (1 << ds->dst->cpu_port)));
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+
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+ /*
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+ * Port Association Vector: when learning source addresses
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+ * of packets, add the address to the address database using
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+ * a port bitmap that has only the bit for this port set and
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+ * the other bits clear.
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+ */
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+ REG_WRITE(addr, 0x0b, 1 << p);
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+
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+ return 0;
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+}
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+
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+static int mv88e6063_setup(struct dsa_switch *ds)
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+{
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+ int i;
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+ int ret;
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+
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+ ret = mv88e6063_switch_reset(ds);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* @@@ initialise atu */
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+
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+ ret = mv88e6063_setup_global(ds);
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+ if (ret < 0)
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+ return ret;
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+
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+ for (i = 0; i < NUM_PORTS; i++) {
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+ ret = mv88e6063_setup_port(ds, i);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr)
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+{
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+ REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
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+ REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
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+ REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
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+
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+ return 0;
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+}
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+
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+static int mv88e6063_port_to_phy_addr(int port)
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+{
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+ if (port >= 0 && port <= NUM_PORTS)
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+ return REG_PHY(port);
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+ return -1;
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+}
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+
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+static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum)
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+{
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+ int addr;
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+
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+ addr = mv88e6063_port_to_phy_addr(port);
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+ if (addr == -1)
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+ return 0xffff;
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+
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+ return reg_read(ds, addr, regnum);
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+}
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+
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+static int
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+mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
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+{
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+ int addr;
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+
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+ addr = mv88e6063_port_to_phy_addr(port);
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+ if (addr == -1)
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+ return 0xffff;
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+
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+ return reg_write(ds, addr, regnum, val);
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+}
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+
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+static void mv88e6063_poll_link(struct dsa_switch *ds)
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+{
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+ int i;
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+
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+ for (i = 0; i < DSA_MAX_PORTS; i++) {
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+ struct net_device *dev;
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+ int uninitialized_var(port_status);
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+ int link;
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+ int speed;
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+ int duplex;
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+ int fc;
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+
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+ dev = ds->ports[i];
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+ if (dev == NULL)
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+ continue;
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+
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+ link = 0;
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+ if (dev->flags & IFF_UP) {
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+ port_status = reg_read(ds, REG_PORT(i), 0x00);
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+ if (port_status < 0)
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+ continue;
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+
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+ link = !!(port_status & 0x1000);
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+ }
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+
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+ if (!link) {
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+ if (netif_carrier_ok(dev)) {
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+ printk(KERN_INFO "%s: link down\n", dev->name);
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+ netif_carrier_off(dev);
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+ }
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+ continue;
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+ }
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+
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+ speed = (port_status & 0x0100) ? 100 : 10;
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+ duplex = (port_status & 0x0200) ? 1 : 0;
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+ fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
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+
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+ if (!netif_carrier_ok(dev)) {
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+ printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
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+ "flow control %sabled\n", dev->name,
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+ speed, duplex ? "full" : "half",
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+ fc ? "en" : "dis");
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+ netif_carrier_on(dev);
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+ }
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+ }
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+}
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+
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+static struct dsa_switch_driver mv88e6063_switch_driver = {
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+ .tag_protocol = htons(ETH_P_TRAILER),
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+ .probe = mv88e6063_probe,
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+ .setup = mv88e6063_setup,
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+ .set_addr = mv88e6063_set_addr,
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+ .phy_read = mv88e6063_phy_read,
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+ .phy_write = mv88e6063_phy_write,
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+ .poll_link = mv88e6063_poll_link,
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+};
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+
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+static int __init mv88e6063_init(void)
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+{
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+ register_switch_driver(&mv88e6063_switch_driver);
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+ return 0;
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+}
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+module_init(mv88e6063_init);
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+
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+static void __exit mv88e6063_cleanup(void)
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+{
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+ unregister_switch_driver(&mv88e6063_switch_driver);
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+}
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+module_exit(mv88e6063_cleanup);
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Gabor Juhos