arm-trusted-firmware-stm32: rework patch for the RTC configuration

A patch was added upstream to temporary enable RTC clock configuration only
for STM32MP15 boards. Use this patch instead of reverting commit 03a581e2.
Now for STM32MP135 boards RTC clock configuration is handled by optee-os.

Signed-off-by: Thomas Richard <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/18628
Signed-off-by: Hauke Mehrtens <[email protected]>

package/boot/arm-trusted-firmware-stm32/Makefile

@@ -8,7 +8,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_VERSION:=2.12
-PKG_RELEASE:=1
+PKG_RELEASE:=2
 
 PKG_HASH:=b4c047493cac1152203e1ba121ae57267e4899b7bf56eb365e22a933342d31c9
 PKG_MAINTAINER:=Thomas Richard <[email protected]>

package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch → package/boot/arm-trusted-firmware-stm32/patches/0001-fix-stm32mp1-fdts-re-enable-RTC-clock.patch

@@ -1,33 +1,18 @@
-From 0e1a71d84585ec33b479c2cb8c8d65a4f6734dbe Mon Sep 17 00:00:00 2001
-From: Thomas Richard <thomas.richard@bootlin.com>
-Date: Wed, 4 Dec 2024 14:26:52 +0100
-Subject: [PATCH] Revert "feat(stm32mp1-fdts): remove RTC clock configuration"
+From 33573ea6842198cfdb5b3fdd320db9e2045855e9 Mon Sep 17 00:00:00 2001
+From: Valentin Caron <[email protected].com>
+Date: Wed, 11 Dec 2024 11:20:04 +0100
+Subject: [PATCH] fix(stm32mp1-fdts): re-enable RTC clock
 
-This reverts commit 703a581e2522bffe21b421c98994dc02aed2934c.
+On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
+yet. Re-enable it temporary to get LSE as clock source of RTC.
+
+Signed-off-by: Valentin Caron <[email protected]>
+Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
 ---
- fdts/stm32mp135f-dk.dts   | 2 ++
  fdts/stm32mp157c-ed1.dts  | 2 ++
  fdts/stm32mp15xx-dkx.dtsi | 2 ++
- 3 files changed, 6 insertions(+)
+ 2 files changed, 4 insertions(+)
 
---- a/fdts/stm32mp135f-dk.dts
-+++ b/fdts/stm32mp135f-dk.dts
-@@ -190,6 +190,7 @@
- 		CLK_AXI_PLL2P
- 		CLK_MLAHBS_PLL3
- 		CLK_CKPER_HSE
-+		CLK_RTC_LSE
- 		CLK_SDMMC1_PLL4P
- 		CLK_SDMMC2_PLL4P
- 		CLK_STGEN_HSE
-@@ -211,6 +212,7 @@
- 		DIV(DIV_APB4, 1)
- 		DIV(DIV_APB5, 2)
- 		DIV(DIV_APB6, 1)
-+		DIV(DIV_RTC, 0)
- 	>;
- 
- 	st,pll_vco {
 --- a/fdts/stm32mp157c-ed1.dts
 +++ b/fdts/stm32mp157c-ed1.dts
 @@ -194,6 +194,7 @@