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@@ -0,0 +1,480 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Author: Mikhail Zhilkin <[email protected]>
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+ */
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+
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+/dts-v1/;
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+#include "mt7987a.dtsi"
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/leds/common.h>
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+
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+/ {
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+ model = "Routerich BE7200";
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+ compatible = "routerich,be7200",
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+ "mediatek,mt7987a",
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+ "mediatek,mt7987";
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+
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+ aliases {
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+ label-mac-device = &gmac1;
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+
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+ led-boot = &led_status_blue;
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+ led-failsafe = &led_status_blue;
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+ led-running = &led_status_blue;
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+ led-upgrade = &led_status_blue;
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+
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyS0,115200n1 \
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+ earlycon=uart8250,mmio32,0x11000000 \
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+ pci=pcie_bus_perf";
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+ rootdisk = <&ubi_fit>;
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+
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+ button-0 {
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+ label = "mesh";
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+ /* Reassigned to RF_KILL */
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+ linux,code = <KEY_RFKILL>;
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+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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+ debounce-interval = <10>;
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+ };
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+
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+ button-1 {
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+ label = "reset";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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+ debounce-interval = <10>;
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+ };
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+ };
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+
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+ gpio-leds {
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+ compatible = "gpio-leds";
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+
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+ led_status_blue: led-0 {
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+ color = <LED_COLOR_ID_BLUE>;
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&pio 4 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-1 {
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+ color = <LED_COLOR_ID_BLUE>;
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+ function = LED_FUNCTION_WLAN_5GHZ;
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+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-2 {
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+ color = <LED_COLOR_ID_BLUE>;
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+ function = "mesh";
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+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-3 {
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+ color = <LED_COLOR_ID_RED>;
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+ function = LED_FUNCTION_WAN;
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+ gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ led-4 {
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+ color = <LED_COLOR_ID_BLUE>;
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+ function = LED_FUNCTION_WAN;
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+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-5 {
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+ color = <LED_COLOR_ID_BLUE>;
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+ function = LED_FUNCTION_LAN;
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+ function-enumerator = <3>;
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+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-6 {
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+ color = <LED_COLOR_ID_BLUE>;
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+ function = LED_FUNCTION_LAN;
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+ function-enumerator = <2>;
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+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-7 {
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+ color = <LED_COLOR_ID_BLUE>;
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+ function = LED_FUNCTION_LAN;
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+ function-enumerator = <1>;
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+ gpios = <&pio 12 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ memory@40000000 {
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+ reg = <0x0 0x40000000 0x0 0x40000000>;
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+ device_type = "memory";
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-name = "fixed-3.3V";
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+ };
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+
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+ reg_usb_5v: regulator-usb-5v {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&pio 14 GPIO_ACTIVE_HIGH>;
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+ regulator-boot-on;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-name = "usb-5v";
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+ };
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+
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+ usb-power {
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+ compatible = "regulator-output";
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+ vout-supply = <®_usb_5v>;
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+ };
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+};
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+
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+&gmac0 {
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+ phy-mode = "2500base-x";
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+ status = "okay";
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+
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+ nvmem-cell-names = "mac-address";
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+ nvmem-cells = <&macaddr_factory_4 (-1)>;
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+};
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+
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+&gmac1 {
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+ openwrt,netdev-name = "wan";
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+ phy-mode = "internal";
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+ phy-handle = <&phy15>;
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+ status = "okay";
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+
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+ nvmem-cell-names = "mac-address";
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+ nvmem-cells = <&macaddr_factory_4 (-2)>;
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+};
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+
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+&mdio {
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+ an8855: mfd@1 {
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+ compatible = "airoha,an8855-mfd";
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+ reg = <1>;
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+ };
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+
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+ phy15: phy@15 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ reg = <15>;
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+
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+ pinctrl-0 = <&i2p5gbe_led0_pins>;
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+ pinctrl-names = "i2p5gbe-led";
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+ };
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+};
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+
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+&an8855 {
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+ efuse {
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+ compatible = "airoha,an8855-efuse";
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+ #nvmem-cell-cells = <0>;
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+
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+ nvmem-layout {
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+ compatible = "fixed-layout";
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
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+ reg = <0xc 0x4>;
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+ };
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+
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+ shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
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+ reg = <0x10 0x4>;
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+ };
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+
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+ shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
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+ reg = <0x14 0x4>;
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+ };
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+
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+ shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
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+ reg = <0x18 0x4>;
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+ };
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+
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+ shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
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+ reg = <0x1c 0x4>;
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+ };
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+
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+ shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
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+ reg = <0x20 0x4>;
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+ };
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+
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+ shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
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+ reg = <0x24 0x4>;
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+ };
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+
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+ shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
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+ reg = <0x28 0x4>;
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+ };
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+
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+ shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
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+ reg = <0x2c 0x4>;
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+ };
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+
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+ shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
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+ reg = <0x30 0x4>;
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+ };
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+
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+ shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
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+ reg = <0x34 0x4>;
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+ };
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+
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+ shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
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+ reg = <0x38 0x4>;
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+ };
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+ };
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+ };
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+
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+ ethernet-switch {
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+ compatible = "airoha,an8855-switch";
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+ reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
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+ airoha,ext-surge;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan1";
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+ phy-mode = "internal";
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+ phy-handle = <&internal_phy1>;
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan2";
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+ phy-mode = "internal";
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+ phy-handle = <&internal_phy2>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan3";
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+ phy-mode = "internal";
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+ phy-handle = <&internal_phy3>;
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ ethernet = <&gmac0>;
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+ phy-mode = "2500base-x";
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+ };
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+ };
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+
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+ mdio {
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+ compatible = "airoha,an8855-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ internal_phy1: phy@1 {
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+ reg = <1>;
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+
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+ nvmem-cells = <&shift_sel_port0_tx_a>,
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+ <&shift_sel_port0_tx_b>,
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+ <&shift_sel_port0_tx_c>,
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+ <&shift_sel_port0_tx_d>;
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+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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+ };
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+
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+ internal_phy2: phy@2 {
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+ reg = <2>;
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+
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+ nvmem-cells = <&shift_sel_port1_tx_a>,
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+ <&shift_sel_port1_tx_b>,
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+ <&shift_sel_port1_tx_c>,
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+ <&shift_sel_port1_tx_d>;
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+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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+ };
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+
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+ internal_phy3: phy@3 {
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+ reg = <3>;
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+
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+ nvmem-cells = <&shift_sel_port2_tx_a>,
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+ <&shift_sel_port2_tx_b>,
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+ <&shift_sel_port2_tx_c>,
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+ <&shift_sel_port2_tx_d>;
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+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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+ };
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+ };
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+};
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+
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+&pcie0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie0_pins>;
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+ reset-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+
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+ pcie@0,0 {
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+ reg = <0x0000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ mt7992@0,0 {
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+ compatible = "mediatek,mt76";
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+ reg = <0x0000 0 0 0 0>;
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+
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+ nvmem-cells = <&eeprom_factory_0>;
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+ nvmem-cell-names = "eeprom";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ieee80211-freq-limit = <2400000 2500000>,
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+ <5170000 5835000>;
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+
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+ band@0 {
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+ reg = <0>;
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+ nvmem-cells = <&macaddr_factory_4 (0)>;
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+ nvmem-cell-names = "mac-address";
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+ };
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+
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+ band@1 {
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+ reg = <1>;
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+ nvmem-cells = <&macaddr_factory_4 (1)>;
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+ nvmem-cell-names = "mac-address";
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+ };
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+ };
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+ };
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+};
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+
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+&pcie1 {
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+ status = "disabled";
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+};
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+
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+&spi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0_flash_pins>;
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+
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+ spi-cal-enable;
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+ spi-cal-mode = "read-data";
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+ spi-cal-datalen = <7>;
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+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4e 0x41 0x4e 0x44>;
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+ spi-cal-addrlen = <5>;
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+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
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+
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+ spi-max-frequency = <52000000>;
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+ spi-tx-bus-width = <4>;
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+ spi-rx-bus-width = <4>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "BL2";
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+ reg = <0x0 0x100000>;
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+ read-only;
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+ };
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+
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+ partition@100000 {
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+ label = "u-boot-env (stock bootloader)";
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+ reg = <0x100000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@180000 {
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+ label = "Factory";
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+ reg = <0x180000 0x400000>;
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+ read-only;
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+
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+ nvmem-layout {
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+ compatible = "fixed-layout";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ eeprom_factory_0: eeprom@0 {
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+ reg = <0x0 0x1e00>;
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+ };
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+
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+ macaddr_factory_4: macaddr@4 {
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+ compatible = "mac-base";
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+ reg = <0x4 0x6>;
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+ #nvmem-cell-cells = <1>;
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+ };
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+ };
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+ };
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+
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+ partition@580000 {
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+ label = "FIP";
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+ reg = <0x580000 0x200000>;
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+ read-only;
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+ };
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+
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+ partition@780000 {
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+ label = "ubi";
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+ reg = <0x780000 0x1f880000>;
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+ compatible = "linux,ubi";
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+
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+ volumes {
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|
|
+ ubi_env: ubi-volume-ubootenv {
|
|
|
+ volname = "ubootenv";
|
|
|
+ };
|
|
|
+
|
|
|
+ ubi_env2: ubi-volume-ubootenv2 {
|
|
|
+ volname = "ubootenv2";
|
|
|
+ };
|
|
|
+
|
|
|
+ ubi_fit: ubi-volume-fit {
|
|
|
+ volname = "fit";
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&ssusb {
|
|
|
+ status = "okay";
|
|
|
+
|
|
|
+ vusb33-supply = <®_3p3v>;
|
|
|
+ vbus-supply = <®_usb_5v>;
|
|
|
+};
|
|
|
+
|
|
|
+&tphyu3port0 {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&uart0 {
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&uart0_pins>;
|
|
|
+
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&ubi_env {
|
|
|
+ nvmem-layout {
|
|
|
+ compatible = "u-boot,env-redundant-bool-layout";
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&ubi_env2 {
|
|
|
+ nvmem-layout {
|
|
|
+ compatible = "u-boot,env-redundant-bool-layout";
|
|
|
+ };
|
|
|
+};
|
Mikhail Zhilkin