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@@ -247,3 +247,40 @@
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{
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return 0;
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}
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+--- a/Documentation/devicetree/bindings/bus/bcma.txt
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++++ b/Documentation/devicetree/bindings/bus/bcma.txt
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+@@ -8,6 +8,11 @@ Required properties:
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+
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+ The cores on the AXI bus are automatically detected by bcma with the
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+ memory ranges they are using and they get registered afterwards.
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++Automatic detection of the IRQ number is not working on
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++BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
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++them manually through device tree. Use an interrupt-map to specify the
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++IRQ used by the devices on the bus. The first address is just an index,
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++because we do not have any special register.
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+
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+ The top-level axi bus may contain children representing attached cores
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+ (devices). This is needed since some hardware details can't be auto
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+@@ -22,6 +27,22 @@ Example:
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+ ranges = <0x00000000 0x18000000 0x00100000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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++ #interrupt-cells = <1>;
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++ interrupt-map-mask = <0x000fffff 0xffff>;
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++ interrupt-map =
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++ /* Ethernet Controller 0 */
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++ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* Ethernet Controller 1 */
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++ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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++
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++ /* PCIe Controller 0 */
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++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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+
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+ chipcommon {
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+ reg = <0x00000000 0x1000>;
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Rafał Miłecki