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@@ -281,6 +281,7 @@
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#define AR8327_PAD_PHYX_GMII_EN BIT(16)
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#define AR8327_PAD_PHYX_RGMII_EN BIT(17)
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#define AR8327_PAD_PHYX_MII_EN BIT(18)
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+#define AR8327_PAD_SGMII_DELAY_EN BIT(19)
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#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2)
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#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20
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#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2)
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