generic: backport upstream v6.16 Realtek PHY patches

83d962316128 net: phy: realtek: add RTL8127-internal PHY
708686132ba0 net: phy: realtek: Add support for PHY LEDs on RTL8211E
be1cc96ddf82 net: phy: realtek: use __set_bit() in rtl8211f_led_hw_control_get()
8c4d0172657c net: phy: realtek: Group RTL82* macro definitions
12d40df259e3 net: phy: realtek: add RTL8211F register defines
7c6fa3ffd265 net: phy: realtek: Clean up RTL821x ExtPage access
f3b265358b91 net: phy: realtek: remove unsed RTL821x_PHYSR* macros
7840e4d6f48a net: phy: realtek: Add support for WOL magic packet on RTL8211F

Signed-off-by: Álvaro Fernández Rojas <[email protected]>

target/linux/generic/backport-6.12/781-20-v6.16-net-phy-realtek-Add-support-for-WOL-magic-packet-on.patch

@@ -0,0 +1,126 @@
+From 7840e4d6f48a75413470935ebdc4bab4fc0c035e Mon Sep 17 00:00:00 2001
+From: Daniel Braunwarth <[email protected]>
+Date: Tue, 29 Apr 2025 13:33:37 +0200
+Subject: [PATCH] net: phy: realtek: Add support for WOL magic packet on
+ RTL8211F
+
+The RTL8211F supports multiple WOL modes. This patch adds support for
+magic packets.
+
+The PHY notifies the system via the INTB/PMEB pin when a WOL event
+occurs.
+
+Signed-off-by: Daniel Braunwarth <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 69 ++++++++++++++++++++++++++
+ 1 file changed, 69 insertions(+)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -10,6 +10,7 @@
+ #include <linux/bitops.h>
+ #include <linux/of.h>
+ #include <linux/phy.h>
++#include <linux/netdevice.h>
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
+@@ -38,6 +39,24 @@
+ 
+ #define RTL8211F_INSR				0x1d
+ 
++/* RTL8211F WOL interrupt configuration */
++#define RTL8211F_INTBCR_PAGE			0xd40
++#define RTL8211F_INTBCR				0x16
++#define RTL8211F_INTBCR_INTB_PMEB		BIT(5)
++
++/* RTL8211F WOL settings */
++#define RTL8211F_WOL_SETTINGS_PAGE		0xd8a
++#define RTL8211F_WOL_SETTINGS_EVENTS		16
++#define RTL8211F_WOL_EVENT_MAGIC		BIT(12)
++#define RTL8211F_WOL_SETTINGS_STATUS		17
++#define RTL8211F_WOL_STATUS_RESET		(BIT(15) | 0x1fff)
++
++/* RTL8211F Unique phyiscal and multicast address (WOL) */
++#define RTL8211F_PHYSICAL_ADDR_PAGE		0xd8c
++#define RTL8211F_PHYSICAL_ADDR_WORD0		16
++#define RTL8211F_PHYSICAL_ADDR_WORD1		17
++#define RTL8211F_PHYSICAL_ADDR_WORD2		18
++
+ #define RTL8211F_LEDCR				0x10
+ #define RTL8211F_LEDCR_MODE			BIT(15)
+ #define RTL8211F_LEDCR_ACT_TXRX			BIT(4)
+@@ -123,6 +142,7 @@ struct rtl821x_priv {
+ 	u16 phycr2;
+ 	bool has_phycr2;
+ 	struct clk *clk;
++	u32 saved_wolopts;
+ };
+ 
+ static int rtl821x_read_page(struct phy_device *phydev)
+@@ -354,6 +374,53 @@ static irqreturn_t rtl8211f_handle_inter
+ 	return IRQ_HANDLED;
+ }
+ 
++static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
++{
++	wol->supported = WAKE_MAGIC;
++	if (phy_read_paged(dev, RTL8211F_WOL_SETTINGS_PAGE, RTL8211F_WOL_SETTINGS_EVENTS)
++	    & RTL8211F_WOL_EVENT_MAGIC)
++		wol->wolopts = WAKE_MAGIC;
++}
++
++static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
++{
++	const u8 *mac_addr = dev->attached_dev->dev_addr;
++	int oldpage;
++
++	oldpage = phy_save_page(dev);
++	if (oldpage < 0)
++		goto err;
++
++	if (wol->wolopts & WAKE_MAGIC) {
++		/* Store the device address for the magic packet */
++		rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE);
++		__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0]));
++		__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2]));
++		__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4]));
++
++		/* Enable magic packet matching and reset WOL status */
++		rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET);
++
++		/* Enable the WOL interrupt */
++		rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE);
++		__phy_set_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB);
++	} else {
++		/* Disable the WOL interrupt */
++		rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE);
++		__phy_clear_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB);
++
++		/* Disable magic packet matching and reset WOL status */
++		rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET);
++	}
++
++err:
++	return phy_restore_page(dev, oldpage, 0);
++}
++
+ static int rtl8211_config_aneg(struct phy_device *phydev)
+ {
+ 	int ret;
+@@ -1400,6 +1467,8 @@ static struct phy_driver realtek_drvs[]
+ 		.read_status	= rtlgen_read_status,
+ 		.config_intr	= &rtl8211f_config_intr,
+ 		.handle_interrupt = rtl8211f_handle_interrupt,
++		.set_wol	= rtl8211f_set_wol,
++		.get_wol	= rtl8211f_get_wol,
+ 		.suspend	= rtl821x_suspend,
+ 		.resume		= rtl821x_resume,
+ 		.read_page	= rtl821x_read_page,

target/linux/generic/backport-6.12/781-21-v6.16-net-phy-realtek-remove-unsed-RTL821x_PHYSR-macros.patch

@@ -0,0 +1,28 @@
+From f3b265358b911fe9e495619bdfa7797749474f95 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:11 +0200
+Subject: [PATCH] net: phy: realtek: remove unsed RTL821x_PHYSR* macros
+
+These macros have there since the first revision but were never used, so
+let's just remove them.
+
+Signed-off-by: Michael Klein <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -18,10 +18,6 @@
+ 
+ #include "realtek.h"
+ 
+-#define RTL821x_PHYSR				0x11
+-#define RTL821x_PHYSR_DUPLEX			BIT(13)
+-#define RTL821x_PHYSR_SPEED			GENMASK(15, 14)
+-
+ #define RTL821x_INER				0x12
+ #define RTL8211B_INER_INIT			0x6400
+ #define RTL8211E_INER_LINK_STATUS		BIT(10)

target/linux/generic/backport-6.12/781-22-v6.16-net-phy-realtek-Clean-up-RTL821x-ExtPage-access.patch

@@ -0,0 +1,95 @@
+From 7c6fa3ffd2650347b1d37f028e232e53d617c1af Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:12 +0200
+Subject: [PATCH] net: phy: realtek: Clean up RTL821x ExtPage access
+
+Factor out RTL8211E extension page access code to
+rtl821x_modify_ext_page() and clean up rtl8211e_config_init()
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 38 ++++++++++++++++----------
+ 1 file changed, 23 insertions(+), 15 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -26,7 +26,9 @@
+ #define RTL821x_INSR				0x13
+ 
+ #define RTL821x_EXT_PAGE_SELECT			0x1e
++
+ #define RTL821x_PAGE_SELECT			0x1f
++#define RTL821x_SET_EXT_PAGE			0x07
+ 
+ #define RTL8211F_PHYCR1				0x18
+ #define RTL8211F_PHYCR2				0x19
+@@ -69,9 +71,12 @@
+ #define RTL8211F_ALDPS_ENABLE			BIT(2)
+ #define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
+ 
++#define RTL8211E_RGMII_EXT_PAGE			0xa4
++#define RTL8211E_RGMII_DELAY			0x1c
+ #define RTL8211E_CTRL_DELAY			BIT(13)
+ #define RTL8211E_TX_DELAY			BIT(12)
+ #define RTL8211E_RX_DELAY			BIT(11)
++#define RTL8211E_DELAY_MASK			GENMASK(13, 11)
+ 
+ #define RTL8201F_ISR				0x1e
+ #define RTL8201F_ISR_ANERR			BIT(15)
+@@ -151,6 +156,21 @@ static int rtl821x_write_page(struct phy
+ 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
+ }
+ 
++static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page,
++				   u32 regnum, u16 mask, u16 set)
++{
++	int oldpage, ret = 0;
++
++	oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
++	if (oldpage >= 0) {
++		ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page);
++		if (ret == 0)
++			ret = __phy_modify(phydev, regnum, mask, set);
++	}
++
++	return phy_restore_page(phydev, oldpage, ret);
++}
++
+ static int rtl821x_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -670,7 +690,6 @@ static int rtl8211f_led_hw_control_set(s
+ 
+ static int rtl8211e_config_init(struct phy_device *phydev)
+ {
+-	int ret = 0, oldpage;
+ 	u16 val;
+ 
+ 	/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
+@@ -700,20 +719,9 @@ static int rtl8211e_config_init(struct p
+ 	 * 12 = RX Delay, 11 = TX Delay
+ 	 * 10:0 = Test && debug settings reserved by realtek
+ 	 */
+-	oldpage = phy_select_page(phydev, 0x7);
+-	if (oldpage < 0)
+-		goto err_restore_page;
+-
+-	ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
+-	if (ret)
+-		goto err_restore_page;
+-
+-	ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
+-			   | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
+-			   val);
+-
+-err_restore_page:
+-	return phy_restore_page(phydev, oldpage, ret);
++	return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE,
++				       RTL8211E_RGMII_DELAY,
++				       RTL8211E_DELAY_MASK, val);
+ }
+ 
+ static int rtl8211b_suspend(struct phy_device *phydev)

target/linux/generic/backport-6.12/781-23-v6.16-net-phy-realtek-add-RTL8211F-register-defines.patch

@@ -0,0 +1,139 @@
+From 12d40df259e38851a0d973535e6023b33e2ea4f9 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:13 +0200
+Subject: [PATCH] net: phy: realtek: add RTL8211F register defines
+
+Add some more defines for RTL8211F page and register numbers.
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 34 ++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -30,11 +30,14 @@
+ #define RTL821x_PAGE_SELECT			0x1f
+ #define RTL821x_SET_EXT_PAGE			0x07
+ 
++/* RTL8211F PHY configuration */
++#define RTL8211F_PHYCR_PAGE			0xa43
+ #define RTL8211F_PHYCR1				0x18
+ #define RTL8211F_PHYCR2				0x19
+ #define RTL8211F_CLKOUT_EN			BIT(0)
+ #define RTL8211F_PHYCR2_PHY_EEE_ENABLE		BIT(5)
+ 
++#define RTL8211F_INSR_PAGE			0xa43
+ #define RTL8211F_INSR				0x1d
+ 
+ /* RTL8211F WOL interrupt configuration */
+@@ -55,6 +58,8 @@
+ #define RTL8211F_PHYSICAL_ADDR_WORD1		17
+ #define RTL8211F_PHYSICAL_ADDR_WORD2		18
+ 
++/* RTL8211F LED configuration */
++#define RTL8211F_LEDCR_PAGE			0xd04
+ #define RTL8211F_LEDCR				0x10
+ #define RTL8211F_LEDCR_MODE			BIT(15)
+ #define RTL8211F_LEDCR_ACT_TXRX			BIT(4)
+@@ -64,7 +69,13 @@
+ #define RTL8211F_LEDCR_MASK			GENMASK(4, 0)
+ #define RTL8211F_LEDCR_SHIFT			5
+ 
++/* RTL8211F RGMII configuration */
++#define RTL8211F_RGMII_PAGE			0xd08
++
++#define RTL8211F_TXCR				0x11
+ #define RTL8211F_TX_DELAY			BIT(8)
++
++#define RTL8211F_RXCR				0x15
+ #define RTL8211F_RX_DELAY			BIT(3)
+ 
+ #define RTL8211F_ALDPS_PLL_OFF			BIT(1)
+@@ -187,7 +198,7 @@ static int rtl821x_probe(struct phy_devi
+ 		return dev_err_probe(dev, PTR_ERR(priv->clk),
+ 				     "failed to get phy clock\n");
+ 
+-	ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
++	ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -197,7 +208,7 @@ static int rtl821x_probe(struct phy_devi
+ 
+ 	priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
+ 	if (priv->has_phycr2) {
+-		ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
++		ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2);
+ 		if (ret < 0)
+ 			return ret;
+ 
+@@ -233,7 +244,7 @@ static int rtl8211f_ack_interrupt(struct
+ {
+ 	int err;
+ 
+-	err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
++	err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
+ 
+ 	return (err < 0) ? err : 0;
+ }
+@@ -376,7 +387,7 @@ static irqreturn_t rtl8211f_handle_inter
+ {
+ 	int irq_status;
+ 
+-	irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
++	irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
+ 	if (irq_status < 0) {
+ 		phy_error(phydev);
+ 		return IRQ_NONE;
+@@ -473,7 +484,7 @@ static int rtl8211f_config_init(struct p
+ 	u16 val_txdly, val_rxdly;
+ 	int ret;
+ 
+-	ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
++	ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1,
+ 				       RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
+ 				       priv->phycr1);
+ 	if (ret < 0) {
+@@ -507,7 +518,8 @@ static int rtl8211f_config_init(struct p
+ 		return 0;
+ 	}
+ 
+-	ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
++	ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
++				       RTL8211F_TXCR, RTL8211F_TX_DELAY,
+ 				       val_txdly);
+ 	if (ret < 0) {
+ 		dev_err(dev, "Failed to update the TX delay register\n");
+@@ -522,7 +534,8 @@ static int rtl8211f_config_init(struct p
+ 			str_enabled_disabled(val_txdly));
+ 	}
+ 
+-	ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
++	ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
++				       RTL8211F_RXCR, RTL8211F_RX_DELAY,
+ 				       val_rxdly);
+ 	if (ret < 0) {
+ 		dev_err(dev, "Failed to update the RX delay register\n");
+@@ -538,14 +551,15 @@ static int rtl8211f_config_init(struct p
+ 	}
+ 
+ 	/* Disable PHY-mode EEE so LPI is passed to the MAC */
+-	ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
++	ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2,
+ 			       RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0);
+ 	if (ret)
+ 		return ret;
+ 
+ 	if (priv->has_phycr2) {
+-		ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
+-				       RTL8211F_CLKOUT_EN, priv->phycr2);
++		ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE,
++				       RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN,
++				       priv->phycr2);
+ 		if (ret < 0) {
+ 			dev_err(dev, "clkout configuration failed: %pe\n",
+ 				ERR_PTR(ret));

target/linux/generic/backport-6.12/781-24-v6.16-net-phy-realtek-Group-RTL82-macro-definitions.patch

@@ -0,0 +1,123 @@
+From 8c4d0172657c1f2d86b9c19172150abcd0e35c39 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:14 +0200
+Subject: [PATCH] net: phy: realtek: Group RTL82* macro definitions
+
+Group macro definitions by PHY in lexicographic order. Within each PHY
+block, definitions are order by page number and then register number.
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 72 +++++++++++++-------------
+ 1 file changed, 37 insertions(+), 35 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -18,6 +18,16 @@
+ 
+ #include "realtek.h"
+ 
++#define RTL8201F_IER				0x13
++
++#define RTL8201F_ISR				0x1e
++#define RTL8201F_ISR_ANERR			BIT(15)
++#define RTL8201F_ISR_DUPLEX			BIT(13)
++#define RTL8201F_ISR_LINK			BIT(11)
++#define RTL8201F_ISR_MASK			(RTL8201F_ISR_ANERR | \
++						 RTL8201F_ISR_DUPLEX | \
++						 RTL8201F_ISR_LINK)
++
+ #define RTL821x_INER				0x12
+ #define RTL8211B_INER_INIT			0x6400
+ #define RTL8211E_INER_LINK_STATUS		BIT(10)
+@@ -30,9 +40,21 @@
+ #define RTL821x_PAGE_SELECT			0x1f
+ #define RTL821x_SET_EXT_PAGE			0x07
+ 
++/* RTL8211E extension page 164/0xa4 */
++#define RTL8211E_RGMII_EXT_PAGE			0xa4
++#define RTL8211E_RGMII_DELAY			0x1c
++#define RTL8211E_CTRL_DELAY			BIT(13)
++#define RTL8211E_TX_DELAY			BIT(12)
++#define RTL8211E_RX_DELAY			BIT(11)
++#define RTL8211E_DELAY_MASK			GENMASK(13, 11)
++
+ /* RTL8211F PHY configuration */
+ #define RTL8211F_PHYCR_PAGE			0xa43
+ #define RTL8211F_PHYCR1				0x18
++#define RTL8211F_ALDPS_PLL_OFF			BIT(1)
++#define RTL8211F_ALDPS_ENABLE			BIT(2)
++#define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
++
+ #define RTL8211F_PHYCR2				0x19
+ #define RTL8211F_CLKOUT_EN			BIT(0)
+ #define RTL8211F_PHYCR2_PHY_EEE_ENABLE		BIT(5)
+@@ -40,24 +62,6 @@
+ #define RTL8211F_INSR_PAGE			0xa43
+ #define RTL8211F_INSR				0x1d
+ 
+-/* RTL8211F WOL interrupt configuration */
+-#define RTL8211F_INTBCR_PAGE			0xd40
+-#define RTL8211F_INTBCR				0x16
+-#define RTL8211F_INTBCR_INTB_PMEB		BIT(5)
+-
+-/* RTL8211F WOL settings */
+-#define RTL8211F_WOL_SETTINGS_PAGE		0xd8a
+-#define RTL8211F_WOL_SETTINGS_EVENTS		16
+-#define RTL8211F_WOL_EVENT_MAGIC		BIT(12)
+-#define RTL8211F_WOL_SETTINGS_STATUS		17
+-#define RTL8211F_WOL_STATUS_RESET		(BIT(15) | 0x1fff)
+-
+-/* RTL8211F Unique phyiscal and multicast address (WOL) */
+-#define RTL8211F_PHYSICAL_ADDR_PAGE		0xd8c
+-#define RTL8211F_PHYSICAL_ADDR_WORD0		16
+-#define RTL8211F_PHYSICAL_ADDR_WORD1		17
+-#define RTL8211F_PHYSICAL_ADDR_WORD2		18
+-
+ /* RTL8211F LED configuration */
+ #define RTL8211F_LEDCR_PAGE			0xd04
+ #define RTL8211F_LEDCR				0x10
+@@ -78,25 +82,23 @@
+ #define RTL8211F_RXCR				0x15
+ #define RTL8211F_RX_DELAY			BIT(3)
+ 
+-#define RTL8211F_ALDPS_PLL_OFF			BIT(1)
+-#define RTL8211F_ALDPS_ENABLE			BIT(2)
+-#define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
++/* RTL8211F WOL interrupt configuration */
++#define RTL8211F_INTBCR_PAGE			0xd40
++#define RTL8211F_INTBCR				0x16
++#define RTL8211F_INTBCR_INTB_PMEB		BIT(5)
+ 
+-#define RTL8211E_RGMII_EXT_PAGE			0xa4
+-#define RTL8211E_RGMII_DELAY			0x1c
+-#define RTL8211E_CTRL_DELAY			BIT(13)
+-#define RTL8211E_TX_DELAY			BIT(12)
+-#define RTL8211E_RX_DELAY			BIT(11)
+-#define RTL8211E_DELAY_MASK			GENMASK(13, 11)
++/* RTL8211F WOL settings */
++#define RTL8211F_WOL_SETTINGS_PAGE		0xd8a
++#define RTL8211F_WOL_SETTINGS_EVENTS		16
++#define RTL8211F_WOL_EVENT_MAGIC		BIT(12)
++#define RTL8211F_WOL_SETTINGS_STATUS		17
++#define RTL8211F_WOL_STATUS_RESET		(BIT(15) | 0x1fff)
+ 
+-#define RTL8201F_ISR				0x1e
+-#define RTL8201F_ISR_ANERR			BIT(15)
+-#define RTL8201F_ISR_DUPLEX			BIT(13)
+-#define RTL8201F_ISR_LINK			BIT(11)
+-#define RTL8201F_ISR_MASK			(RTL8201F_ISR_ANERR | \
+-						 RTL8201F_ISR_DUPLEX | \
+-						 RTL8201F_ISR_LINK)
+-#define RTL8201F_IER				0x13
++/* RTL8211F Unique phyiscal and multicast address (WOL) */
++#define RTL8211F_PHYSICAL_ADDR_PAGE		0xd8c
++#define RTL8211F_PHYSICAL_ADDR_WORD0		16
++#define RTL8211F_PHYSICAL_ADDR_WORD1		17
++#define RTL8211F_PHYSICAL_ADDR_WORD2		18
+ 
+ #define RTL822X_VND1_SERDES_OPTION			0x697a
+ #define RTL822X_VND1_SERDES_OPTION_MODE_MASK		GENMASK(5, 0)

target/linux/generic/backport-6.12/781-25-v6.16-net-phy-realtek-use-__set_bit-in-rtl8211f_led_hw_con.patch

@@ -0,0 +1,42 @@
+From be1cc96ddf82bb0c0a159751f73239d6d3e9594a Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:15 +0200
+Subject: [PATCH] net: phy: realtek: use __set_bit() in
+ rtl8211f_led_hw_control_get()
+
+rtl8211f_led_hw_control_get() does not need atomic bit operations,
+replace set_bit() by __set_bit().
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -659,17 +659,17 @@ static int rtl8211f_led_hw_control_get(s
+ 	val &= RTL8211F_LEDCR_MASK;
+ 
+ 	if (val & RTL8211F_LEDCR_LINK_10)
+-		set_bit(TRIGGER_NETDEV_LINK_10, rules);
++		__set_bit(TRIGGER_NETDEV_LINK_10, rules);
+ 
+ 	if (val & RTL8211F_LEDCR_LINK_100)
+-		set_bit(TRIGGER_NETDEV_LINK_100, rules);
++		__set_bit(TRIGGER_NETDEV_LINK_100, rules);
+ 
+ 	if (val & RTL8211F_LEDCR_LINK_1000)
+-		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++		__set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+ 
+ 	if (val & RTL8211F_LEDCR_ACT_TXRX) {
+-		set_bit(TRIGGER_NETDEV_RX, rules);
+-		set_bit(TRIGGER_NETDEV_TX, rules);
++		__set_bit(TRIGGER_NETDEV_RX, rules);
++		__set_bit(TRIGGER_NETDEV_TX, rules);
+ 	}
+ 
+ 	return 0;

target/linux/generic/backport-6.12/781-26-v6.16-net-phy-realtek-Add-support-for-PHY-LEDs-on-RTL8211E.patch

@@ -0,0 +1,215 @@
+From 708686132ba02659267c0cebcc414348ece389a5 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:16 +0200
+Subject: [PATCH] net: phy: realtek: Add support for PHY LEDs on RTL8211E
+
+Like the RTL8211F, the RTL8211E PHY supports up to three LEDs.
+Add netdev trigger support for them, too.
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 125 +++++++++++++++++++++++--
+ 1 file changed, 119 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -40,6 +40,20 @@
+ #define RTL821x_PAGE_SELECT			0x1f
+ #define RTL821x_SET_EXT_PAGE			0x07
+ 
++/* RTL8211E extension page 44/0x2c */
++#define RTL8211E_LEDCR_EXT_PAGE			0x2c
++#define RTL8211E_LEDCR1				0x1a
++#define RTL8211E_LEDCR1_ACT_TXRX		BIT(4)
++#define RTL8211E_LEDCR1_MASK			BIT(4)
++#define RTL8211E_LEDCR1_SHIFT			1
++
++#define RTL8211E_LEDCR2				0x1c
++#define RTL8211E_LEDCR2_LINK_1000		BIT(2)
++#define RTL8211E_LEDCR2_LINK_100		BIT(1)
++#define RTL8211E_LEDCR2_LINK_10			BIT(0)
++#define RTL8211E_LEDCR2_MASK			GENMASK(2, 0)
++#define RTL8211E_LEDCR2_SHIFT			4
++
+ /* RTL8211E extension page 164/0xa4 */
+ #define RTL8211E_RGMII_EXT_PAGE			0xa4
+ #define RTL8211E_RGMII_DELAY			0x1c
+@@ -145,7 +159,8 @@
+ #define RTL_8221B_VN_CG				0x001cc84a
+ #define RTL_8251B				0x001cc862
+ 
+-#define RTL8211F_LED_COUNT			3
++/* RTL8211E and RTL8211F support up to three LEDs */
++#define RTL8211x_LED_COUNT			3
+ 
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+@@ -169,6 +184,21 @@ static int rtl821x_write_page(struct phy
+ 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
+ }
+ 
++static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page,
++				 u32 regnum)
++{
++	int oldpage, ret = 0;
++
++	oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
++	if (oldpage >= 0) {
++		ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page);
++		if (ret == 0)
++			ret = __phy_read(phydev, regnum);
++	}
++
++	return phy_restore_page(phydev, oldpage, ret);
++}
++
+ static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page,
+ 				   u32 regnum, u16 mask, u16 set)
+ {
+@@ -608,7 +638,7 @@ static int rtl821x_resume(struct phy_dev
+ 	return 0;
+ }
+ 
+-static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
++static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ 					unsigned long rules)
+ {
+ 	const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
+@@ -627,9 +657,11 @@ static int rtl8211f_led_hw_is_supported(
+ 	 *      rates and Active indication always at all three 10+100+1000
+ 	 *      link rates.
+ 	 * This code currently uses mode B only.
++	 *
++	 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B.
+ 	 */
+ 
+-	if (index >= RTL8211F_LED_COUNT)
++	if (index >= RTL8211x_LED_COUNT)
+ 		return -EINVAL;
+ 
+ 	/* Filter out any other unsupported triggers. */
+@@ -648,7 +680,7 @@ static int rtl8211f_led_hw_control_get(s
+ {
+ 	int val;
+ 
+-	if (index >= RTL8211F_LED_COUNT)
++	if (index >= RTL8211x_LED_COUNT)
+ 		return -EINVAL;
+ 
+ 	val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
+@@ -681,7 +713,7 @@ static int rtl8211f_led_hw_control_set(s
+ 	const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
+ 	u16 reg = 0;
+ 
+-	if (index >= RTL8211F_LED_COUNT)
++	if (index >= RTL8211x_LED_COUNT)
+ 		return -EINVAL;
+ 
+ 	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+@@ -704,6 +736,84 @@ static int rtl8211f_led_hw_control_set(s
+ 	return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
+ }
+ 
++static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index,
++				       unsigned long *rules)
++{
++	int ret;
++	u16 cr1, cr2;
++
++	if (index >= RTL8211x_LED_COUNT)
++		return -EINVAL;
++
++	ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				    RTL8211E_LEDCR1);
++	if (ret < 0)
++		return ret;
++
++	cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index;
++	if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) {
++		__set_bit(TRIGGER_NETDEV_RX, rules);
++		__set_bit(TRIGGER_NETDEV_TX, rules);
++	}
++
++	ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				    RTL8211E_LEDCR2);
++	if (ret < 0)
++		return ret;
++
++	cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index;
++	if (cr2 & RTL8211E_LEDCR2_LINK_10)
++		__set_bit(TRIGGER_NETDEV_LINK_10, rules);
++
++	if (cr2 & RTL8211E_LEDCR2_LINK_100)
++		__set_bit(TRIGGER_NETDEV_LINK_100, rules);
++
++	if (cr2 & RTL8211E_LEDCR2_LINK_1000)
++		__set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++
++	return ret;
++}
++
++static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	const u16 cr1mask =
++		RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index);
++	const u16 cr2mask =
++		RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index);
++	u16 cr1 = 0, cr2 = 0;
++	int ret;
++
++	if (index >= RTL8211x_LED_COUNT)
++		return -EINVAL;
++
++	if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
++	    test_bit(TRIGGER_NETDEV_TX, &rules)) {
++		cr1 |= RTL8211E_LEDCR1_ACT_TXRX;
++	}
++
++	cr1 <<= RTL8211E_LEDCR1_SHIFT * index;
++	ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				      RTL8211E_LEDCR1, cr1mask, cr1);
++	if (ret < 0)
++		return ret;
++
++	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++		cr2 |= RTL8211E_LEDCR2_LINK_10;
++
++	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++		cr2 |= RTL8211E_LEDCR2_LINK_100;
++
++	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++		cr2 |= RTL8211E_LEDCR2_LINK_1000;
++
++	cr2 <<= RTL8211E_LEDCR2_SHIFT * index;
++	ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				      RTL8211E_LEDCR2, cr2mask, cr2);
++
++	return ret;
++}
++
+ static int rtl8211e_config_init(struct phy_device *phydev)
+ {
+ 	u16 val;
+@@ -1479,6 +1589,9 @@ static struct phy_driver realtek_drvs[]
+ 		.resume		= genphy_resume,
+ 		.read_page	= rtl821x_read_page,
+ 		.write_page	= rtl821x_write_page,
++		.led_hw_is_supported = rtl8211x_led_hw_is_supported,
++		.led_hw_control_get = rtl8211e_led_hw_control_get,
++		.led_hw_control_set = rtl8211e_led_hw_control_set,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc916),
+ 		.name		= "RTL8211F Gigabit Ethernet",
+@@ -1494,7 +1607,7 @@ static struct phy_driver realtek_drvs[]
+ 		.read_page	= rtl821x_read_page,
+ 		.write_page	= rtl821x_write_page,
+ 		.flags		= PHY_ALWAYS_CALL_SUSPEND,
+-		.led_hw_is_supported = rtl8211f_led_hw_is_supported,
++		.led_hw_is_supported = rtl8211x_led_hw_is_supported,
+ 		.led_hw_control_get = rtl8211f_led_hw_control_get,
+ 		.led_hw_control_set = rtl8211f_led_hw_control_set,
+ 	}, {

target/linux/generic/backport-6.12/781-27-v6.16-net-phy-realtek-add-RTL8127-internal-PHY.patch

@@ -0,0 +1,35 @@
+From 83d9623161283f5f6883ee3fdb88ef2177b8a5f1 Mon Sep 17 00:00:00 2001
+From: ChunHao Lin <[email protected]>
+Date: Fri, 16 May 2025 13:56:22 +0800
+Subject: [PATCH] net: phy: realtek: add RTL8127-internal PHY
+
+RTL8127-internal PHY is RTL8261C which is a integrated 10Gbps PHY with ID
+0x001cc890. It follows the code path of RTL8125/RTL8126 internal NBase-T
+PHY.
+
+Signed-off-by: ChunHao Lin <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -158,6 +158,7 @@
+ #define RTL_8221B_VB_CG				0x001cc849
+ #define RTL_8221B_VN_CG				0x001cc84a
+ #define RTL_8251B				0x001cc862
++#define RTL_8261C				0x001cc890
+ 
+ /* RTL8211E and RTL8211F support up to three LEDs */
+ #define RTL8211x_LED_COUNT			3
+@@ -1370,6 +1371,7 @@ static int rtl_internal_nbaset_match_phy
+ 	case RTL_GENERIC_PHYID:
+ 	case RTL_8221B:
+ 	case RTL_8251B:
++	case RTL_8261C:
+ 	case 0x001cc841:
+ 		break;
+ 	default:

target/linux/generic/backport-6.6/781-34-v6.16-net-phy-realtek-Add-support-for-WOL-magic-packet-on.patch

@@ -0,0 +1,126 @@
+From 7840e4d6f48a75413470935ebdc4bab4fc0c035e Mon Sep 17 00:00:00 2001
+From: Daniel Braunwarth <[email protected]>
+Date: Tue, 29 Apr 2025 13:33:37 +0200
+Subject: [PATCH] net: phy: realtek: Add support for WOL magic packet on
+ RTL8211F
+
+The RTL8211F supports multiple WOL modes. This patch adds support for
+magic packets.
+
+The PHY notifies the system via the INTB/PMEB pin when a WOL event
+occurs.
+
+Signed-off-by: Daniel Braunwarth <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 69 ++++++++++++++++++++++++++
+ 1 file changed, 69 insertions(+)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -10,6 +10,7 @@
+ #include <linux/bitops.h>
+ #include <linux/of.h>
+ #include <linux/phy.h>
++#include <linux/netdevice.h>
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
+@@ -38,6 +39,24 @@
+ 
+ #define RTL8211F_INSR				0x1d
+ 
++/* RTL8211F WOL interrupt configuration */
++#define RTL8211F_INTBCR_PAGE			0xd40
++#define RTL8211F_INTBCR				0x16
++#define RTL8211F_INTBCR_INTB_PMEB		BIT(5)
++
++/* RTL8211F WOL settings */
++#define RTL8211F_WOL_SETTINGS_PAGE		0xd8a
++#define RTL8211F_WOL_SETTINGS_EVENTS		16
++#define RTL8211F_WOL_EVENT_MAGIC		BIT(12)
++#define RTL8211F_WOL_SETTINGS_STATUS		17
++#define RTL8211F_WOL_STATUS_RESET		(BIT(15) | 0x1fff)
++
++/* RTL8211F Unique phyiscal and multicast address (WOL) */
++#define RTL8211F_PHYSICAL_ADDR_PAGE		0xd8c
++#define RTL8211F_PHYSICAL_ADDR_WORD0		16
++#define RTL8211F_PHYSICAL_ADDR_WORD1		17
++#define RTL8211F_PHYSICAL_ADDR_WORD2		18
++
+ #define RTL8211F_LEDCR				0x10
+ #define RTL8211F_LEDCR_MODE			BIT(15)
+ #define RTL8211F_LEDCR_ACT_TXRX			BIT(4)
+@@ -123,6 +142,7 @@ struct rtl821x_priv {
+ 	u16 phycr2;
+ 	bool has_phycr2;
+ 	struct clk *clk;
++	u32 saved_wolopts;
+ };
+ 
+ static int rtl821x_read_page(struct phy_device *phydev)
+@@ -354,6 +374,53 @@ static irqreturn_t rtl8211f_handle_inter
+ 	return IRQ_HANDLED;
+ }
+ 
++static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
++{
++	wol->supported = WAKE_MAGIC;
++	if (phy_read_paged(dev, RTL8211F_WOL_SETTINGS_PAGE, RTL8211F_WOL_SETTINGS_EVENTS)
++	    & RTL8211F_WOL_EVENT_MAGIC)
++		wol->wolopts = WAKE_MAGIC;
++}
++
++static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
++{
++	const u8 *mac_addr = dev->attached_dev->dev_addr;
++	int oldpage;
++
++	oldpage = phy_save_page(dev);
++	if (oldpage < 0)
++		goto err;
++
++	if (wol->wolopts & WAKE_MAGIC) {
++		/* Store the device address for the magic packet */
++		rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE);
++		__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0]));
++		__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2]));
++		__phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4]));
++
++		/* Enable magic packet matching and reset WOL status */
++		rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET);
++
++		/* Enable the WOL interrupt */
++		rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE);
++		__phy_set_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB);
++	} else {
++		/* Disable the WOL interrupt */
++		rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE);
++		__phy_clear_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB);
++
++		/* Disable magic packet matching and reset WOL status */
++		rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0);
++		__phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET);
++	}
++
++err:
++	return phy_restore_page(dev, oldpage, 0);
++}
++
+ static int rtl8211_config_aneg(struct phy_device *phydev)
+ {
+ 	int ret;
+@@ -1400,6 +1467,8 @@ static struct phy_driver realtek_drvs[]
+ 		.read_status	= rtlgen_read_status,
+ 		.config_intr	= &rtl8211f_config_intr,
+ 		.handle_interrupt = rtl8211f_handle_interrupt,
++		.set_wol	= rtl8211f_set_wol,
++		.get_wol	= rtl8211f_get_wol,
+ 		.suspend	= rtl821x_suspend,
+ 		.resume		= rtl821x_resume,
+ 		.read_page	= rtl821x_read_page,

target/linux/generic/backport-6.6/781-35-v6.16-net-phy-realtek-remove-unsed-RTL821x_PHYSR-macros.patch

@@ -0,0 +1,28 @@
+From f3b265358b911fe9e495619bdfa7797749474f95 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:11 +0200
+Subject: [PATCH] net: phy: realtek: remove unsed RTL821x_PHYSR* macros
+
+These macros have there since the first revision but were never used, so
+let's just remove them.
+
+Signed-off-by: Michael Klein <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -18,10 +18,6 @@
+ 
+ #include "realtek.h"
+ 
+-#define RTL821x_PHYSR				0x11
+-#define RTL821x_PHYSR_DUPLEX			BIT(13)
+-#define RTL821x_PHYSR_SPEED			GENMASK(15, 14)
+-
+ #define RTL821x_INER				0x12
+ #define RTL8211B_INER_INIT			0x6400
+ #define RTL8211E_INER_LINK_STATUS		BIT(10)

target/linux/generic/backport-6.6/781-36-v6.16-net-phy-realtek-Clean-up-RTL821x-ExtPage-access.patch

@@ -0,0 +1,95 @@
+From 7c6fa3ffd2650347b1d37f028e232e53d617c1af Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:12 +0200
+Subject: [PATCH] net: phy: realtek: Clean up RTL821x ExtPage access
+
+Factor out RTL8211E extension page access code to
+rtl821x_modify_ext_page() and clean up rtl8211e_config_init()
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 38 ++++++++++++++++----------
+ 1 file changed, 23 insertions(+), 15 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -26,7 +26,9 @@
+ #define RTL821x_INSR				0x13
+ 
+ #define RTL821x_EXT_PAGE_SELECT			0x1e
++
+ #define RTL821x_PAGE_SELECT			0x1f
++#define RTL821x_SET_EXT_PAGE			0x07
+ 
+ #define RTL8211F_PHYCR1				0x18
+ #define RTL8211F_PHYCR2				0x19
+@@ -69,9 +71,12 @@
+ #define RTL8211F_ALDPS_ENABLE			BIT(2)
+ #define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
+ 
++#define RTL8211E_RGMII_EXT_PAGE			0xa4
++#define RTL8211E_RGMII_DELAY			0x1c
+ #define RTL8211E_CTRL_DELAY			BIT(13)
+ #define RTL8211E_TX_DELAY			BIT(12)
+ #define RTL8211E_RX_DELAY			BIT(11)
++#define RTL8211E_DELAY_MASK			GENMASK(13, 11)
+ 
+ #define RTL8201F_ISR				0x1e
+ #define RTL8201F_ISR_ANERR			BIT(15)
+@@ -151,6 +156,21 @@ static int rtl821x_write_page(struct phy
+ 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
+ }
+ 
++static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page,
++				   u32 regnum, u16 mask, u16 set)
++{
++	int oldpage, ret = 0;
++
++	oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
++	if (oldpage >= 0) {
++		ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page);
++		if (ret == 0)
++			ret = __phy_modify(phydev, regnum, mask, set);
++	}
++
++	return phy_restore_page(phydev, oldpage, ret);
++}
++
+ static int rtl821x_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -670,7 +690,6 @@ static int rtl8211f_led_hw_control_set(s
+ 
+ static int rtl8211e_config_init(struct phy_device *phydev)
+ {
+-	int ret = 0, oldpage;
+ 	u16 val;
+ 
+ 	/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
+@@ -700,20 +719,9 @@ static int rtl8211e_config_init(struct p
+ 	 * 12 = RX Delay, 11 = TX Delay
+ 	 * 10:0 = Test && debug settings reserved by realtek
+ 	 */
+-	oldpage = phy_select_page(phydev, 0x7);
+-	if (oldpage < 0)
+-		goto err_restore_page;
+-
+-	ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
+-	if (ret)
+-		goto err_restore_page;
+-
+-	ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
+-			   | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
+-			   val);
+-
+-err_restore_page:
+-	return phy_restore_page(phydev, oldpage, ret);
++	return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE,
++				       RTL8211E_RGMII_DELAY,
++				       RTL8211E_DELAY_MASK, val);
+ }
+ 
+ static int rtl8211b_suspend(struct phy_device *phydev)

target/linux/generic/backport-6.6/781-37-v6.16-net-phy-realtek-add-RTL8211F-register-defines.patch

@@ -0,0 +1,139 @@
+From 12d40df259e38851a0d973535e6023b33e2ea4f9 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:13 +0200
+Subject: [PATCH] net: phy: realtek: add RTL8211F register defines
+
+Add some more defines for RTL8211F page and register numbers.
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 34 ++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -30,11 +30,14 @@
+ #define RTL821x_PAGE_SELECT			0x1f
+ #define RTL821x_SET_EXT_PAGE			0x07
+ 
++/* RTL8211F PHY configuration */
++#define RTL8211F_PHYCR_PAGE			0xa43
+ #define RTL8211F_PHYCR1				0x18
+ #define RTL8211F_PHYCR2				0x19
+ #define RTL8211F_CLKOUT_EN			BIT(0)
+ #define RTL8211F_PHYCR2_PHY_EEE_ENABLE		BIT(5)
+ 
++#define RTL8211F_INSR_PAGE			0xa43
+ #define RTL8211F_INSR				0x1d
+ 
+ /* RTL8211F WOL interrupt configuration */
+@@ -55,6 +58,8 @@
+ #define RTL8211F_PHYSICAL_ADDR_WORD1		17
+ #define RTL8211F_PHYSICAL_ADDR_WORD2		18
+ 
++/* RTL8211F LED configuration */
++#define RTL8211F_LEDCR_PAGE			0xd04
+ #define RTL8211F_LEDCR				0x10
+ #define RTL8211F_LEDCR_MODE			BIT(15)
+ #define RTL8211F_LEDCR_ACT_TXRX			BIT(4)
+@@ -64,7 +69,13 @@
+ #define RTL8211F_LEDCR_MASK			GENMASK(4, 0)
+ #define RTL8211F_LEDCR_SHIFT			5
+ 
++/* RTL8211F RGMII configuration */
++#define RTL8211F_RGMII_PAGE			0xd08
++
++#define RTL8211F_TXCR				0x11
+ #define RTL8211F_TX_DELAY			BIT(8)
++
++#define RTL8211F_RXCR				0x15
+ #define RTL8211F_RX_DELAY			BIT(3)
+ 
+ #define RTL8211F_ALDPS_PLL_OFF			BIT(1)
+@@ -187,7 +198,7 @@ static int rtl821x_probe(struct phy_devi
+ 		return dev_err_probe(dev, PTR_ERR(priv->clk),
+ 				     "failed to get phy clock\n");
+ 
+-	ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
++	ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -197,7 +208,7 @@ static int rtl821x_probe(struct phy_devi
+ 
+ 	priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
+ 	if (priv->has_phycr2) {
+-		ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
++		ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2);
+ 		if (ret < 0)
+ 			return ret;
+ 
+@@ -233,7 +244,7 @@ static int rtl8211f_ack_interrupt(struct
+ {
+ 	int err;
+ 
+-	err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
++	err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
+ 
+ 	return (err < 0) ? err : 0;
+ }
+@@ -376,7 +387,7 @@ static irqreturn_t rtl8211f_handle_inter
+ {
+ 	int irq_status;
+ 
+-	irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
++	irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
+ 	if (irq_status < 0) {
+ 		phy_error(phydev);
+ 		return IRQ_NONE;
+@@ -473,7 +484,7 @@ static int rtl8211f_config_init(struct p
+ 	u16 val_txdly, val_rxdly;
+ 	int ret;
+ 
+-	ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
++	ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1,
+ 				       RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
+ 				       priv->phycr1);
+ 	if (ret < 0) {
+@@ -507,7 +518,8 @@ static int rtl8211f_config_init(struct p
+ 		return 0;
+ 	}
+ 
+-	ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
++	ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
++				       RTL8211F_TXCR, RTL8211F_TX_DELAY,
+ 				       val_txdly);
+ 	if (ret < 0) {
+ 		dev_err(dev, "Failed to update the TX delay register\n");
+@@ -522,7 +534,8 @@ static int rtl8211f_config_init(struct p
+ 			str_enabled_disabled(val_txdly));
+ 	}
+ 
+-	ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
++	ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
++				       RTL8211F_RXCR, RTL8211F_RX_DELAY,
+ 				       val_rxdly);
+ 	if (ret < 0) {
+ 		dev_err(dev, "Failed to update the RX delay register\n");
+@@ -538,14 +551,15 @@ static int rtl8211f_config_init(struct p
+ 	}
+ 
+ 	/* Disable PHY-mode EEE so LPI is passed to the MAC */
+-	ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
++	ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2,
+ 			       RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0);
+ 	if (ret)
+ 		return ret;
+ 
+ 	if (priv->has_phycr2) {
+-		ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
+-				       RTL8211F_CLKOUT_EN, priv->phycr2);
++		ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE,
++				       RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN,
++				       priv->phycr2);
+ 		if (ret < 0) {
+ 			dev_err(dev, "clkout configuration failed: %pe\n",
+ 				ERR_PTR(ret));

target/linux/generic/backport-6.6/781-38-v6.16-net-phy-realtek-Group-RTL82-macro-definitions.patch

@@ -0,0 +1,123 @@
+From 8c4d0172657c1f2d86b9c19172150abcd0e35c39 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:14 +0200
+Subject: [PATCH] net: phy: realtek: Group RTL82* macro definitions
+
+Group macro definitions by PHY in lexicographic order. Within each PHY
+block, definitions are order by page number and then register number.
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 72 +++++++++++++-------------
+ 1 file changed, 37 insertions(+), 35 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -18,6 +18,16 @@
+ 
+ #include "realtek.h"
+ 
++#define RTL8201F_IER				0x13
++
++#define RTL8201F_ISR				0x1e
++#define RTL8201F_ISR_ANERR			BIT(15)
++#define RTL8201F_ISR_DUPLEX			BIT(13)
++#define RTL8201F_ISR_LINK			BIT(11)
++#define RTL8201F_ISR_MASK			(RTL8201F_ISR_ANERR | \
++						 RTL8201F_ISR_DUPLEX | \
++						 RTL8201F_ISR_LINK)
++
+ #define RTL821x_INER				0x12
+ #define RTL8211B_INER_INIT			0x6400
+ #define RTL8211E_INER_LINK_STATUS		BIT(10)
+@@ -30,9 +40,21 @@
+ #define RTL821x_PAGE_SELECT			0x1f
+ #define RTL821x_SET_EXT_PAGE			0x07
+ 
++/* RTL8211E extension page 164/0xa4 */
++#define RTL8211E_RGMII_EXT_PAGE			0xa4
++#define RTL8211E_RGMII_DELAY			0x1c
++#define RTL8211E_CTRL_DELAY			BIT(13)
++#define RTL8211E_TX_DELAY			BIT(12)
++#define RTL8211E_RX_DELAY			BIT(11)
++#define RTL8211E_DELAY_MASK			GENMASK(13, 11)
++
+ /* RTL8211F PHY configuration */
+ #define RTL8211F_PHYCR_PAGE			0xa43
+ #define RTL8211F_PHYCR1				0x18
++#define RTL8211F_ALDPS_PLL_OFF			BIT(1)
++#define RTL8211F_ALDPS_ENABLE			BIT(2)
++#define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
++
+ #define RTL8211F_PHYCR2				0x19
+ #define RTL8211F_CLKOUT_EN			BIT(0)
+ #define RTL8211F_PHYCR2_PHY_EEE_ENABLE		BIT(5)
+@@ -40,24 +62,6 @@
+ #define RTL8211F_INSR_PAGE			0xa43
+ #define RTL8211F_INSR				0x1d
+ 
+-/* RTL8211F WOL interrupt configuration */
+-#define RTL8211F_INTBCR_PAGE			0xd40
+-#define RTL8211F_INTBCR				0x16
+-#define RTL8211F_INTBCR_INTB_PMEB		BIT(5)
+-
+-/* RTL8211F WOL settings */
+-#define RTL8211F_WOL_SETTINGS_PAGE		0xd8a
+-#define RTL8211F_WOL_SETTINGS_EVENTS		16
+-#define RTL8211F_WOL_EVENT_MAGIC		BIT(12)
+-#define RTL8211F_WOL_SETTINGS_STATUS		17
+-#define RTL8211F_WOL_STATUS_RESET		(BIT(15) | 0x1fff)
+-
+-/* RTL8211F Unique phyiscal and multicast address (WOL) */
+-#define RTL8211F_PHYSICAL_ADDR_PAGE		0xd8c
+-#define RTL8211F_PHYSICAL_ADDR_WORD0		16
+-#define RTL8211F_PHYSICAL_ADDR_WORD1		17
+-#define RTL8211F_PHYSICAL_ADDR_WORD2		18
+-
+ /* RTL8211F LED configuration */
+ #define RTL8211F_LEDCR_PAGE			0xd04
+ #define RTL8211F_LEDCR				0x10
+@@ -78,25 +82,23 @@
+ #define RTL8211F_RXCR				0x15
+ #define RTL8211F_RX_DELAY			BIT(3)
+ 
+-#define RTL8211F_ALDPS_PLL_OFF			BIT(1)
+-#define RTL8211F_ALDPS_ENABLE			BIT(2)
+-#define RTL8211F_ALDPS_XTAL_OFF			BIT(12)
++/* RTL8211F WOL interrupt configuration */
++#define RTL8211F_INTBCR_PAGE			0xd40
++#define RTL8211F_INTBCR				0x16
++#define RTL8211F_INTBCR_INTB_PMEB		BIT(5)
+ 
+-#define RTL8211E_RGMII_EXT_PAGE			0xa4
+-#define RTL8211E_RGMII_DELAY			0x1c
+-#define RTL8211E_CTRL_DELAY			BIT(13)
+-#define RTL8211E_TX_DELAY			BIT(12)
+-#define RTL8211E_RX_DELAY			BIT(11)
+-#define RTL8211E_DELAY_MASK			GENMASK(13, 11)
++/* RTL8211F WOL settings */
++#define RTL8211F_WOL_SETTINGS_PAGE		0xd8a
++#define RTL8211F_WOL_SETTINGS_EVENTS		16
++#define RTL8211F_WOL_EVENT_MAGIC		BIT(12)
++#define RTL8211F_WOL_SETTINGS_STATUS		17
++#define RTL8211F_WOL_STATUS_RESET		(BIT(15) | 0x1fff)
+ 
+-#define RTL8201F_ISR				0x1e
+-#define RTL8201F_ISR_ANERR			BIT(15)
+-#define RTL8201F_ISR_DUPLEX			BIT(13)
+-#define RTL8201F_ISR_LINK			BIT(11)
+-#define RTL8201F_ISR_MASK			(RTL8201F_ISR_ANERR | \
+-						 RTL8201F_ISR_DUPLEX | \
+-						 RTL8201F_ISR_LINK)
+-#define RTL8201F_IER				0x13
++/* RTL8211F Unique phyiscal and multicast address (WOL) */
++#define RTL8211F_PHYSICAL_ADDR_PAGE		0xd8c
++#define RTL8211F_PHYSICAL_ADDR_WORD0		16
++#define RTL8211F_PHYSICAL_ADDR_WORD1		17
++#define RTL8211F_PHYSICAL_ADDR_WORD2		18
+ 
+ #define RTL822X_VND1_SERDES_OPTION			0x697a
+ #define RTL822X_VND1_SERDES_OPTION_MODE_MASK		GENMASK(5, 0)

target/linux/generic/backport-6.6/781-39-v6.16-net-phy-realtek-use-__set_bit-in-rtl8211f_led_hw_con.patch

@@ -0,0 +1,42 @@
+From be1cc96ddf82bb0c0a159751f73239d6d3e9594a Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:15 +0200
+Subject: [PATCH] net: phy: realtek: use __set_bit() in
+ rtl8211f_led_hw_control_get()
+
+rtl8211f_led_hw_control_get() does not need atomic bit operations,
+replace set_bit() by __set_bit().
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -659,17 +659,17 @@ static int rtl8211f_led_hw_control_get(s
+ 	val &= RTL8211F_LEDCR_MASK;
+ 
+ 	if (val & RTL8211F_LEDCR_LINK_10)
+-		set_bit(TRIGGER_NETDEV_LINK_10, rules);
++		__set_bit(TRIGGER_NETDEV_LINK_10, rules);
+ 
+ 	if (val & RTL8211F_LEDCR_LINK_100)
+-		set_bit(TRIGGER_NETDEV_LINK_100, rules);
++		__set_bit(TRIGGER_NETDEV_LINK_100, rules);
+ 
+ 	if (val & RTL8211F_LEDCR_LINK_1000)
+-		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++		__set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+ 
+ 	if (val & RTL8211F_LEDCR_ACT_TXRX) {
+-		set_bit(TRIGGER_NETDEV_RX, rules);
+-		set_bit(TRIGGER_NETDEV_TX, rules);
++		__set_bit(TRIGGER_NETDEV_RX, rules);
++		__set_bit(TRIGGER_NETDEV_TX, rules);
+ 	}
+ 
+ 	return 0;

target/linux/generic/backport-6.6/781-40-v6.16-net-phy-realtek-Add-support-for-PHY-LEDs-on-RTL8211E.patch

@@ -0,0 +1,215 @@
+From 708686132ba02659267c0cebcc414348ece389a5 Mon Sep 17 00:00:00 2001
+From: Michael Klein <[email protected]>
+Date: Sun, 4 May 2025 19:29:16 +0200
+Subject: [PATCH] net: phy: realtek: Add support for PHY LEDs on RTL8211E
+
+Like the RTL8211F, the RTL8211E PHY supports up to three LEDs.
+Add netdev trigger support for them, too.
+
+Signed-off-by: Michael Klein <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 125 +++++++++++++++++++++++--
+ 1 file changed, 119 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -40,6 +40,20 @@
+ #define RTL821x_PAGE_SELECT			0x1f
+ #define RTL821x_SET_EXT_PAGE			0x07
+ 
++/* RTL8211E extension page 44/0x2c */
++#define RTL8211E_LEDCR_EXT_PAGE			0x2c
++#define RTL8211E_LEDCR1				0x1a
++#define RTL8211E_LEDCR1_ACT_TXRX		BIT(4)
++#define RTL8211E_LEDCR1_MASK			BIT(4)
++#define RTL8211E_LEDCR1_SHIFT			1
++
++#define RTL8211E_LEDCR2				0x1c
++#define RTL8211E_LEDCR2_LINK_1000		BIT(2)
++#define RTL8211E_LEDCR2_LINK_100		BIT(1)
++#define RTL8211E_LEDCR2_LINK_10			BIT(0)
++#define RTL8211E_LEDCR2_MASK			GENMASK(2, 0)
++#define RTL8211E_LEDCR2_SHIFT			4
++
+ /* RTL8211E extension page 164/0xa4 */
+ #define RTL8211E_RGMII_EXT_PAGE			0xa4
+ #define RTL8211E_RGMII_DELAY			0x1c
+@@ -145,7 +159,8 @@
+ #define RTL_8221B_VN_CG				0x001cc84a
+ #define RTL_8251B				0x001cc862
+ 
+-#define RTL8211F_LED_COUNT			3
++/* RTL8211E and RTL8211F support up to three LEDs */
++#define RTL8211x_LED_COUNT			3
+ 
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+@@ -169,6 +184,21 @@ static int rtl821x_write_page(struct phy
+ 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
+ }
+ 
++static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page,
++				 u32 regnum)
++{
++	int oldpage, ret = 0;
++
++	oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
++	if (oldpage >= 0) {
++		ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page);
++		if (ret == 0)
++			ret = __phy_read(phydev, regnum);
++	}
++
++	return phy_restore_page(phydev, oldpage, ret);
++}
++
+ static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page,
+ 				   u32 regnum, u16 mask, u16 set)
+ {
+@@ -608,7 +638,7 @@ static int rtl821x_resume(struct phy_dev
+ 	return 0;
+ }
+ 
+-static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
++static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ 					unsigned long rules)
+ {
+ 	const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
+@@ -627,9 +657,11 @@ static int rtl8211f_led_hw_is_supported(
+ 	 *      rates and Active indication always at all three 10+100+1000
+ 	 *      link rates.
+ 	 * This code currently uses mode B only.
++	 *
++	 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B.
+ 	 */
+ 
+-	if (index >= RTL8211F_LED_COUNT)
++	if (index >= RTL8211x_LED_COUNT)
+ 		return -EINVAL;
+ 
+ 	/* Filter out any other unsupported triggers. */
+@@ -648,7 +680,7 @@ static int rtl8211f_led_hw_control_get(s
+ {
+ 	int val;
+ 
+-	if (index >= RTL8211F_LED_COUNT)
++	if (index >= RTL8211x_LED_COUNT)
+ 		return -EINVAL;
+ 
+ 	val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
+@@ -681,7 +713,7 @@ static int rtl8211f_led_hw_control_set(s
+ 	const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
+ 	u16 reg = 0;
+ 
+-	if (index >= RTL8211F_LED_COUNT)
++	if (index >= RTL8211x_LED_COUNT)
+ 		return -EINVAL;
+ 
+ 	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+@@ -704,6 +736,84 @@ static int rtl8211f_led_hw_control_set(s
+ 	return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
+ }
+ 
++static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index,
++				       unsigned long *rules)
++{
++	int ret;
++	u16 cr1, cr2;
++
++	if (index >= RTL8211x_LED_COUNT)
++		return -EINVAL;
++
++	ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				    RTL8211E_LEDCR1);
++	if (ret < 0)
++		return ret;
++
++	cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index;
++	if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) {
++		__set_bit(TRIGGER_NETDEV_RX, rules);
++		__set_bit(TRIGGER_NETDEV_TX, rules);
++	}
++
++	ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				    RTL8211E_LEDCR2);
++	if (ret < 0)
++		return ret;
++
++	cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index;
++	if (cr2 & RTL8211E_LEDCR2_LINK_10)
++		__set_bit(TRIGGER_NETDEV_LINK_10, rules);
++
++	if (cr2 & RTL8211E_LEDCR2_LINK_100)
++		__set_bit(TRIGGER_NETDEV_LINK_100, rules);
++
++	if (cr2 & RTL8211E_LEDCR2_LINK_1000)
++		__set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++
++	return ret;
++}
++
++static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	const u16 cr1mask =
++		RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index);
++	const u16 cr2mask =
++		RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index);
++	u16 cr1 = 0, cr2 = 0;
++	int ret;
++
++	if (index >= RTL8211x_LED_COUNT)
++		return -EINVAL;
++
++	if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
++	    test_bit(TRIGGER_NETDEV_TX, &rules)) {
++		cr1 |= RTL8211E_LEDCR1_ACT_TXRX;
++	}
++
++	cr1 <<= RTL8211E_LEDCR1_SHIFT * index;
++	ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				      RTL8211E_LEDCR1, cr1mask, cr1);
++	if (ret < 0)
++		return ret;
++
++	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++		cr2 |= RTL8211E_LEDCR2_LINK_10;
++
++	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++		cr2 |= RTL8211E_LEDCR2_LINK_100;
++
++	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++		cr2 |= RTL8211E_LEDCR2_LINK_1000;
++
++	cr2 <<= RTL8211E_LEDCR2_SHIFT * index;
++	ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
++				      RTL8211E_LEDCR2, cr2mask, cr2);
++
++	return ret;
++}
++
+ static int rtl8211e_config_init(struct phy_device *phydev)
+ {
+ 	u16 val;
+@@ -1479,6 +1589,9 @@ static struct phy_driver realtek_drvs[]
+ 		.resume		= genphy_resume,
+ 		.read_page	= rtl821x_read_page,
+ 		.write_page	= rtl821x_write_page,
++		.led_hw_is_supported = rtl8211x_led_hw_is_supported,
++		.led_hw_control_get = rtl8211e_led_hw_control_get,
++		.led_hw_control_set = rtl8211e_led_hw_control_set,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc916),
+ 		.name		= "RTL8211F Gigabit Ethernet",
+@@ -1494,7 +1607,7 @@ static struct phy_driver realtek_drvs[]
+ 		.read_page	= rtl821x_read_page,
+ 		.write_page	= rtl821x_write_page,
+ 		.flags		= PHY_ALWAYS_CALL_SUSPEND,
+-		.led_hw_is_supported = rtl8211f_led_hw_is_supported,
++		.led_hw_is_supported = rtl8211x_led_hw_is_supported,
+ 		.led_hw_control_get = rtl8211f_led_hw_control_get,
+ 		.led_hw_control_set = rtl8211f_led_hw_control_set,
+ 	}, {

target/linux/generic/backport-6.6/781-41-v6.16-net-phy-realtek-add-RTL8127-internal-PHY.patch

@@ -0,0 +1,35 @@
+From 83d9623161283f5f6883ee3fdb88ef2177b8a5f1 Mon Sep 17 00:00:00 2001
+From: ChunHao Lin <[email protected]>
+Date: Fri, 16 May 2025 13:56:22 +0800
+Subject: [PATCH] net: phy: realtek: add RTL8127-internal PHY
+
+RTL8127-internal PHY is RTL8261C which is a integrated 10Gbps PHY with ID
+0x001cc890. It follows the code path of RTL8125/RTL8126 internal NBase-T
+PHY.
+
+Signed-off-by: ChunHao Lin <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/phy/realtek/realtek_main.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/phy/realtek/realtek_main.c
++++ b/drivers/net/phy/realtek/realtek_main.c
+@@ -158,6 +158,7 @@
+ #define RTL_8221B_VB_CG				0x001cc849
+ #define RTL_8221B_VN_CG				0x001cc84a
+ #define RTL_8251B				0x001cc862
++#define RTL_8261C				0x001cc890
+ 
+ /* RTL8211E and RTL8211F support up to three LEDs */
+ #define RTL8211x_LED_COUNT			3
+@@ -1370,6 +1371,7 @@ static int rtl_internal_nbaset_match_phy
+ 	case RTL_GENERIC_PHYID:
+ 	case RTL_8221B:
+ 	case RTL_8251B:
++	case RTL_8261C:
+ 	case 0x001cc841:
+ 		break;
+ 	default:

target/linux/generic/pending-6.12/720-01-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1434,6 +1434,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1638,6 +1638,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.name		= "RTL8226 2.5Gbps PHY",
  		.match_phy_device = rtl8226_match_phy_device,
@@ -23,7 +23,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features	= rtl822x_get_features,
  		.config_aneg	= rtl822x_config_aneg,
  		.read_status	= rtl822x_read_status,
-@@ -1444,6 +1445,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1648,6 +1649,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_match_phy_device,
  		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
@@ -31,7 +31,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features	= rtl822x_get_features,
  		.config_aneg	= rtl822x_config_aneg,
  		.config_init    = rtl822xb_config_init,
-@@ -1456,6 +1458,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1660,6 +1662,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		PHY_ID_MATCH_EXACT(0x001cc838),
  		.name           = "RTL8226-CG 2.5Gbps PHY",
@@ -39,7 +39,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
  		.read_status    = rtl822x_read_status,
-@@ -1466,6 +1469,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1670,6 +1673,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		PHY_ID_MATCH_EXACT(0x001cc848),
  		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
@@ -47,7 +47,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
  		.config_init    = rtl822xb_config_init,
-@@ -1478,6 +1482,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1682,6 +1686,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
@@ -55,7 +55,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
-@@ -1491,6 +1496,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1695,6 +1700,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
@@ -63,7 +63,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.probe		= rtl822x_probe,
  		.config_init    = rtl822xb_config_init,
  		.get_rate_matching = rtl822xb_get_rate_matching,
-@@ -1502,6 +1508,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1706,6 +1712,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
@@ -71,7 +71,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
-@@ -1515,6 +1522,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1719,6 +1726,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",

target/linux/generic/pending-6.12/720-02-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch

@@ -20,7 +20,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -837,8 +837,8 @@ static int rtl822x_probe(struct phy_devi
+@@ -1035,8 +1035,8 @@ static int rtl822x_probe(struct phy_devi
  static int rtl822xb_config_init(struct phy_device *phydev)
  {
  	bool has_2500, has_sgmii;
@@ -30,7 +30,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  
  	has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
  			    phydev->host_interfaces) ||
-@@ -888,7 +888,29 @@ static int rtl822xb_config_init(struct p
+@@ -1086,7 +1086,29 @@ static int rtl822xb_config_init(struct p
  	if (ret < 0)
  		return ret;
  

target/linux/generic/pending-6.12/720-03-net-phy-realtek-make-sure-paged-read-is-protected-by.patch

@@ -18,7 +18,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1115,9 +1115,11 @@ static bool rtlgen_supports_2_5gbps(stru
+@@ -1313,9 +1313,11 @@ static bool rtlgen_supports_2_5gbps(stru
  {
  	int val;
  

target/linux/generic/pending-6.12/720-04-net-phy-realtek-setup-aldps.patch

@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -82,6 +82,10 @@
+@@ -129,6 +129,10 @@
   */
  #define RTL822X_VND2_C22_REG(reg)		(0xa400 + 2 * (reg))
  
@@ -24,7 +24,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  #define RTL8366RB_POWER_SAVE			0x15
  #define RTL8366RB_POWER_SAVE_ON			BIT(12)
  
-@@ -892,6 +896,15 @@ static int rtl822xb_config_init(struct p
+@@ -1090,6 +1094,15 @@ static int rtl822xb_config_init(struct p
  	if (ret < 0)
  		return ret;
  

target/linux/generic/pending-6.12/720-05-net-phy-realtek-detect-early-version-of-RTL8221B.patch

@@ -14,7 +14,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 Signed-off-by: Mieczyslaw Nalewaj <[email protected]>
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1170,10 +1170,32 @@ static int rtl8226_match_phy_device(stru
+@@ -1368,10 +1368,32 @@ static int rtl8226_match_phy_device(stru
  static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
  			       bool is_c45)
  {

target/linux/generic/pending-6.12/720-06-net-phy-realtek-support-interrupt-of-RTL8221B.patch

@@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1381,6 +1381,51 @@ static irqreturn_t rtl9000a_handle_inter
+@@ -1580,6 +1580,51 @@ static irqreturn_t rtl9000a_handle_inter
  	return IRQ_HANDLED;
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  static struct phy_driver realtek_drvs[] = {
  	{
  		PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1541,6 +1586,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1745,6 +1790,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
@@ -73,7 +73,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
-@@ -1555,6 +1602,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1759,6 +1806,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
@@ -82,7 +82,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
  		.config_init    = rtl822xb_config_init,
-@@ -1567,6 +1616,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1771,6 +1820,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
@@ -91,7 +91,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
-@@ -1581,6 +1632,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1785,6 +1836,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",

target/linux/generic/pending-6.12/720-07-net-phy-realtek-mark-existing-MMDs-as-present.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1046,6 +1046,9 @@ static int rtl822x_c45_get_features(stru
+@@ -1244,6 +1244,9 @@ static int rtl822x_c45_get_features(stru
  	linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
  			 phydev->supported);
  

target/linux/generic/pending-6.12/720-08-net-phy-realtek-work-around-broken-serdes.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 ---
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -926,6 +926,22 @@ static int rtl822xb_config_init(struct p
+@@ -1124,6 +1124,22 @@ static int rtl822xb_config_init(struct p
  	return 0;
  }
  
@@ -38,7 +38,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  static int rtl822xb_get_rate_matching(struct phy_device *phydev,
  				      phy_interface_t iface)
  {
-@@ -1609,7 +1625,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1813,7 +1829,7 @@ static struct phy_driver realtek_drvs[]
  		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
@@ -47,7 +47,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_rate_matching = rtl822xb_get_rate_matching,
  		.get_features   = rtl822x_c45_get_features,
  		.config_aneg    = rtl822x_c45_config_aneg,
-@@ -1639,7 +1655,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1843,7 +1859,7 @@ static struct phy_driver realtek_drvs[]
  		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,

target/linux/generic/pending-6.12/720-09-net-phy-realtek-disable-MDIO-broadcast.patch

@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 ---
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -852,6 +852,11 @@ static int rtl822xb_config_init(struct p
+@@ -1050,6 +1050,11 @@ static int rtl822xb_config_init(struct p
  			     phydev->host_interfaces) ||
  		    phydev->interface == PHY_INTERFACE_MODE_SGMII;
  

target/linux/generic/pending-6.6/720-01-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1434,6 +1434,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1638,6 +1638,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.name		= "RTL8226 2.5Gbps PHY",
  		.match_phy_device = rtl8226_match_phy_device,
@@ -23,7 +23,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features	= rtl822x_get_features,
  		.config_aneg	= rtl822x_config_aneg,
  		.read_status	= rtl822x_read_status,
-@@ -1444,6 +1445,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1648,6 +1649,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_match_phy_device,
  		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
@@ -31,7 +31,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features	= rtl822x_get_features,
  		.config_aneg	= rtl822x_config_aneg,
  		.config_init    = rtl822xb_config_init,
-@@ -1456,6 +1458,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1660,6 +1662,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		PHY_ID_MATCH_EXACT(0x001cc838),
  		.name           = "RTL8226-CG 2.5Gbps PHY",
@@ -39,7 +39,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
  		.read_status    = rtl822x_read_status,
-@@ -1466,6 +1469,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1670,6 +1673,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		PHY_ID_MATCH_EXACT(0x001cc848),
  		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
@@ -47,7 +47,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
  		.config_init    = rtl822xb_config_init,
-@@ -1478,6 +1482,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1682,6 +1686,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
@@ -55,7 +55,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
-@@ -1491,6 +1496,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1695,6 +1700,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
@@ -63,7 +63,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.probe		= rtl822x_probe,
  		.config_init    = rtl822xb_config_init,
  		.get_rate_matching = rtl822xb_get_rate_matching,
-@@ -1502,6 +1508,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1706,6 +1712,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
@@ -71,7 +71,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
  		.config_aneg    = rtl822x_config_aneg,
-@@ -1515,6 +1522,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1719,6 +1726,7 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",

target/linux/generic/pending-6.6/720-02-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch

@@ -20,7 +20,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -837,8 +837,8 @@ static int rtl822x_probe(struct phy_devi
+@@ -1035,8 +1035,8 @@ static int rtl822x_probe(struct phy_devi
  static int rtl822xb_config_init(struct phy_device *phydev)
  {
  	bool has_2500, has_sgmii;
@@ -30,7 +30,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  
  	has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
  			    phydev->host_interfaces) ||
-@@ -888,7 +888,29 @@ static int rtl822xb_config_init(struct p
+@@ -1086,7 +1086,29 @@ static int rtl822xb_config_init(struct p
  	if (ret < 0)
  		return ret;
  

target/linux/generic/pending-6.6/720-03-net-phy-realtek-make-sure-paged-read-is-protected-by.patch

@@ -18,7 +18,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1115,9 +1115,11 @@ static bool rtlgen_supports_2_5gbps(stru
+@@ -1313,9 +1313,11 @@ static bool rtlgen_supports_2_5gbps(stru
  {
  	int val;
  

target/linux/generic/pending-6.6/720-04-net-phy-realtek-setup-aldps.patch

@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -82,6 +82,10 @@
+@@ -129,6 +129,10 @@
   */
  #define RTL822X_VND2_C22_REG(reg)		(0xa400 + 2 * (reg))
  
@@ -24,7 +24,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  #define RTL8366RB_POWER_SAVE			0x15
  #define RTL8366RB_POWER_SAVE_ON			BIT(12)
  
-@@ -892,6 +896,15 @@ static int rtl822xb_config_init(struct p
+@@ -1090,6 +1094,15 @@ static int rtl822xb_config_init(struct p
  	if (ret < 0)
  		return ret;
  

target/linux/generic/pending-6.6/720-05-net-phy-realtek-detect-early-version-of-RTL8221B.patch

@@ -14,7 +14,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 Signed-off-by: Mieczyslaw Nalewaj <[email protected]>
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1170,10 +1170,32 @@ static int rtl8226_match_phy_device(stru
+@@ -1368,10 +1368,32 @@ static int rtl8226_match_phy_device(stru
  static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
  			       bool is_c45)
  {

target/linux/generic/pending-6.6/720-06-net-phy-realtek-support-interrupt-of-RTL8221B.patch

@@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1381,6 +1381,51 @@ static irqreturn_t rtl9000a_handle_inter
+@@ -1580,6 +1580,51 @@ static irqreturn_t rtl9000a_handle_inter
  	return IRQ_HANDLED;
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  static struct phy_driver realtek_drvs[] = {
  	{
  		PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1541,6 +1586,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1745,6 +1790,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
@@ -73,7 +73,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
-@@ -1555,6 +1602,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1759,6 +1806,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
@@ -82,7 +82,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
  		.config_init    = rtl822xb_config_init,
-@@ -1567,6 +1616,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1771,6 +1820,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
  		.name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
@@ -91,7 +91,7 @@ Signed-off-by: Jianhui Zhao <[email protected]>
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
  		.get_features   = rtl822x_get_features,
-@@ -1581,6 +1632,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1785,6 +1836,8 @@ static struct phy_driver realtek_drvs[]
  	}, {
  		.match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
  		.name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",

target/linux/generic/pending-6.6/720-07-net-phy-realtek-mark-existing-MMDs-as-present.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -1046,6 +1046,9 @@ static int rtl822x_c45_get_features(stru
+@@ -1244,6 +1244,9 @@ static int rtl822x_c45_get_features(stru
  	linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
  			 phydev->supported);
  

target/linux/generic/pending-6.6/720-08-net-phy-realtek-work-around-broken-serdes.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 ---
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -926,6 +926,22 @@ static int rtl822xb_config_init(struct p
+@@ -1124,6 +1124,22 @@ static int rtl822xb_config_init(struct p
  	return 0;
  }
  
@@ -38,7 +38,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  static int rtl822xb_get_rate_matching(struct phy_device *phydev,
  				      phy_interface_t iface)
  {
-@@ -1609,7 +1625,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1813,7 +1829,7 @@ static struct phy_driver realtek_drvs[]
  		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,
@@ -47,7 +47,7 @@ Signed-off-by: Daniel Golle <[email protected]>
  		.get_rate_matching = rtl822xb_get_rate_matching,
  		.get_features   = rtl822x_c45_get_features,
  		.config_aneg    = rtl822x_c45_config_aneg,
-@@ -1639,7 +1655,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1843,7 +1859,7 @@ static struct phy_driver realtek_drvs[]
  		.handle_interrupt = rtl8221b_handle_interrupt,
  		.soft_reset     = genphy_soft_reset,
  		.probe		= rtl822x_probe,

target/linux/generic/pending-6.6/720-09-net-phy-realtek-disable-MDIO-broadcast.patch

@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 ---
 --- a/drivers/net/phy/realtek/realtek_main.c
 +++ b/drivers/net/phy/realtek/realtek_main.c
-@@ -852,6 +852,11 @@ static int rtl822xb_config_init(struct p
+@@ -1050,6 +1050,11 @@ static int rtl822xb_config_init(struct p
  			     phydev->host_interfaces) ||
  		    phydev->interface == PHY_INTERFACE_MODE_SGMII;