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@@ -340,51 +340,56 @@ static int rtl93xx_get_sds(struct phy_device *phydev)
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return sds_num;
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}
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-static void rtl83xx_pcs_get_state(struct phylink_pcs *pcs,
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- struct phylink_link_state *state)
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+static void rtldsa_83xx_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state)
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{
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struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs);
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struct rtl838x_switch_priv *priv = rtpcs->priv;
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int port = rtpcs->port;
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u64 speed;
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- u64 link;
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- if (port < 0 || port > priv->cpu_port) {
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- state->link = false;
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+ state->link = 0;
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+ state->speed = SPEED_UNKNOWN;
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+ state->duplex = DUPLEX_UNKNOWN;
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+ state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
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+
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+ if (port < 0 || port > priv->cpu_port)
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return;
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- }
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- state->link = 0;
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- link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
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- if (link & BIT_ULL(port))
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- state->link = 1;
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- pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
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+ if (!(priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port)))
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+ return;
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+
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+ state->link = 1;
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- state->duplex = 0;
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if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
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- state->duplex = 1;
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+ state->duplex = DUPLEX_FULL;
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+ else
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+ state->duplex = DUPLEX_HALF;
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speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
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- speed >>= (port % 16) << 1;
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- switch (speed & 0x3) {
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- case 0:
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+ speed = (speed >> ((port % 16) << 1)) & 0x3;
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+
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+ switch (speed) {
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+ case RTL_SPEED_10:
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state->speed = SPEED_10;
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break;
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- case 1:
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+ case RTL_SPEED_100:
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state->speed = SPEED_100;
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break;
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- case 2:
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+ case RTL_SPEED_1000:
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state->speed = SPEED_1000;
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break;
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case 3:
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- if (priv->family_id == RTL9300_FAMILY_ID
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- && (port == 24 || port == 26)) /* Internal serdes */
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- state->speed = SPEED_2500;
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- else
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- state->speed = SPEED_100; /* Is in fact 500Mbit */
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+ /*
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+ * This is ok so far but with minor inconsistencies. On RTL838x this setting is
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+ * for either 500M or 2G. It might be that MAC_GLITE_STS register tells more. On
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+ * RTL839x these vendor specifics are derived from MAC_LINK_500M_STS and mode 3
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+ * is 10G. This is of interest so resolve to it. Sadly it is off by one for the
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+ * current RTL_SPEED_10000 (=4) definition for RTL93xx.
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+ */
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+ state->speed = SPEED_10000;
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+ break;
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}
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- state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
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if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
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state->pause |= MLO_PAUSE_RX;
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if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
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@@ -2046,7 +2051,7 @@ static int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_re
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const struct phylink_pcs_ops rtl83xx_pcs_ops = {
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.pcs_an_restart = rtl83xx_pcs_an_restart,
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- .pcs_get_state = rtl83xx_pcs_get_state,
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+ .pcs_get_state = rtldsa_83xx_pcs_get_state,
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.pcs_config = rtl83xx_pcs_config,
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};
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Markus Stockhausen