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@@ -0,0 +1,86 @@
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+--- a/arch/mips/Kconfig
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++++ b/arch/mips/Kconfig
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+@@ -18,6 +18,24 @@
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+ prompt "System type"
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+ default SGI_IP22
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+
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++config AR7
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++ bool "Texas Instruments AR7"
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++ select BOOT_ELF32
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++ select DMA_NONCOHERENT
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++ select CEVT_R4K
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++ select CSRC_R4K
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++ select IRQ_CPU
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++ select NO_EXCEPT_FILL
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++ select SWAP_IO_SPACE
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++ select SYS_HAS_CPU_MIPS32_R1
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++ select SYS_HAS_EARLY_PRINTK
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++ select SYS_SUPPORTS_32BIT_KERNEL
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++ select SYS_SUPPORTS_KGDB
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++ select SYS_SUPPORTS_LITTLE_ENDIAN
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++ select SYS_SUPPORTS_BIG_ENDIAN
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++ select GENERIC_GPIO
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++ select GENERIC_HARDIRQS_NO__DO_IRQ
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++
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+ config MACH_ALCHEMY
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+ bool "Alchemy processor based machines"
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+
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+--- a/arch/mips/kernel/traps.c
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++++ b/arch/mips/kernel/traps.c
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+@@ -1112,9 +1112,22 @@
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+
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+ exception_handlers[n] = handler;
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+ if (n == 0 && cpu_has_divec) {
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+- *(u32 *)(ebase + 0x200) = 0x08000000 |
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+- (0x03ffffff & (handler >> 2));
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+- flush_icache_range(ebase + 0x200, ebase + 0x204);
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++ if ((handler ^ (ebase + 4)) & 0xfc000000) {
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++ /* lui k0, 0x0000 */
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++ *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
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++ /* ori k0, 0x0000 */
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++ *(u32 *)(ebase + 0x204) =
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++ 0x375a0000 | (handler & 0xffff);
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++ /* jr k0 */
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++ *(u32 *)(ebase + 0x208) = 0x03400008;
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++ /* nop */
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++ *(u32 *)(ebase + 0x20C) = 0x00000000;
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++ flush_icache_range(ebase + 0x200, ebase + 0x210);
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++ } else {
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++ *(u32 *)(ebase + 0x200) =
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++ 0x08000000 | (0x03ffffff & (handler >> 2));
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++ flush_icache_range(ebase + 0x200, ebase + 0x204);
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++ }
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+ }
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+ return (void *)old_handler;
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+ }
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+--- a/arch/mips/Makefile
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++++ b/arch/mips/Makefile
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+@@ -167,6 +167,13 @@
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+ #
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+
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+ #
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++# Texas Instruments AR7
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++#
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++core-$(CONFIG_AR7) += arch/mips/ar7/
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++cflags-$(CONFIG_AR7) += -Iinclude/asm-mips/ar7
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++load-$(CONFIG_AR7) += 0xffffffff94100000
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++
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++#
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+ # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
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+ #
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+ core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
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+--- a/include/asm-mips/page.h
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++++ b/include/asm-mips/page.h
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+@@ -182,8 +182,10 @@
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+ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
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+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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+
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+-#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
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+-#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
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++#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \
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++ PHYS_OFFSET)
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++#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
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++ PHYS_OFFSET)
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+
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+ #include <asm-generic/memory_model.h>
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+ #include <asm-generic/page.h>
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