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@@ -510,7 +510,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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return 0;
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}
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-@@ -4580,6 +4727,7 @@ static const struct net_device_ops mtk_n
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+@@ -4596,6 +4743,7 @@ static const struct net_device_ops mtk_n
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static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
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{
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const __be32 *_id = of_get_property(np, "reg", NULL);
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@@ -518,7 +518,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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phy_interface_t phy_mode;
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struct phylink *phylink;
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struct mtk_mac *mac;
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-@@ -4616,16 +4764,41 @@ static int mtk_add_mac(struct mtk_eth *e
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+@@ -4632,16 +4780,41 @@ static int mtk_add_mac(struct mtk_eth *e
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mac->id = id;
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mac->hw = eth;
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mac->of_node = np;
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@@ -568,7 +568,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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}
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memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
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-@@ -4708,8 +4881,21 @@ static int mtk_add_mac(struct mtk_eth *e
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+@@ -4724,8 +4897,21 @@ static int mtk_add_mac(struct mtk_eth *e
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phy_interface_zero(mac->phylink_config.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_INTERNAL,
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mac->phylink_config.supported_interfaces);
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@@ -590,7 +590,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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phylink = phylink_create(&mac->phylink_config,
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of_fwnode_handle(mac->of_node),
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phy_mode, &mtk_phylink_ops);
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-@@ -4760,6 +4946,26 @@ free_netdev:
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+@@ -4776,6 +4962,26 @@ free_netdev:
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return err;
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}
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@@ -617,7 +617,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
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{
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struct net_device *dev, *tmp;
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-@@ -4906,7 +5112,8 @@ static int mtk_probe(struct platform_dev
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+@@ -4922,7 +5128,8 @@ static int mtk_probe(struct platform_dev
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regmap_write(cci, 0, 3);
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}
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@@ -627,7 +627,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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err = mtk_sgmii_init(eth);
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if (err)
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-@@ -5017,6 +5224,24 @@ static int mtk_probe(struct platform_dev
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+@@ -5033,6 +5240,24 @@ static int mtk_probe(struct platform_dev
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}
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}
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@@ -652,7 +652,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
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err = devm_request_irq(eth->dev, eth->irq[0],
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mtk_handle_irq, 0,
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-@@ -5120,6 +5345,11 @@ static int mtk_remove(struct platform_de
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+@@ -5136,6 +5361,11 @@ static int mtk_remove(struct platform_de
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mtk_stop(eth->netdev[i]);
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mac = netdev_priv(eth->netdev[i]);
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phylink_disconnect_phy(mac->phylink);
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@@ -674,7 +674,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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#include <linux/rhashtable.h>
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#include <linux/dim.h>
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#include <linux/bitfield.h>
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-@@ -505,6 +506,21 @@
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+@@ -513,6 +514,21 @@
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#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
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#define INTF_MODE_RGMII_10_100 0
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@@ -696,7 +696,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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/* GPIO port control registers for GMAC 2*/
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#define GPIO_OD33_CTRL8 0x4c0
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#define GPIO_BIAS_CTRL 0xed0
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-@@ -530,6 +546,7 @@
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+@@ -538,6 +554,7 @@
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#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
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#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
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#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
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@@ -704,7 +704,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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/* ethernet subsystem clock register */
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-@@ -568,6 +585,11 @@
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+@@ -576,6 +593,11 @@
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#define GEPHY_MAC_SEL BIT(1)
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/* Top misc registers */
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@@ -716,7 +716,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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#define USB_PHY_SWITCH_REG 0x218
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#define QPHY_SEL_MASK GENMASK(1, 0)
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#define SGMII_QPHY_SEL 0x2
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-@@ -592,6 +614,8 @@
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+@@ -600,6 +622,8 @@
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#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
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#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
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@@ -725,7 +725,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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#define MTK_FE_CDM1_FSM 0x220
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#define MTK_FE_CDM2_FSM 0x224
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#define MTK_FE_CDM3_FSM 0x238
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-@@ -600,6 +624,11 @@
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+@@ -608,6 +632,11 @@
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#define MTK_FE_CDM6_FSM 0x328
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#define MTK_FE_GDM1_FSM 0x228
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#define MTK_FE_GDM2_FSM 0x22C
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@@ -737,7 +737,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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|
|
|
|
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
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|
|
-@@ -724,12 +753,8 @@ enum mtk_clks_map {
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+@@ -732,12 +761,8 @@ enum mtk_clks_map {
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MTK_CLK_ETHWARP_WOCPU2,
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MTK_CLK_ETHWARP_WOCPU1,
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MTK_CLK_ETHWARP_WOCPU0,
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|
@@ -750,7 +750,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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|
MTK_CLK_TOP_ETH_GMII_SEL,
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MTK_CLK_TOP_ETH_REFCK_50M_SEL,
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|
MTK_CLK_TOP_ETH_SYS_200M_SEL,
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|
-@@ -800,19 +825,9 @@ enum mtk_clks_map {
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|
+@@ -808,19 +833,9 @@ enum mtk_clks_map {
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BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
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BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
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|
BIT_ULL(MTK_CLK_CRYPTO) | \
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|
|
@@ -770,7 +770,7 @@ Signed-off-by: Daniel Golle <[email protected]>
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|
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
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|
|
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
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|
|
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
|
|
|
-@@ -946,6 +961,8 @@ enum mkt_eth_capabilities {
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|
|
+@@ -954,6 +969,8 @@ enum mkt_eth_capabilities {
|
|
|
MTK_RGMII_BIT = 0,
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|
|
MTK_TRGMII_BIT,
|
|
|
MTK_SGMII_BIT,
|
|
|
@@ -779,7 +779,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
MTK_ESW_BIT,
|
|
|
MTK_GEPHY_BIT,
|
|
|
MTK_MUX_BIT,
|
|
|
-@@ -966,8 +983,11 @@ enum mkt_eth_capabilities {
|
|
|
+@@ -974,8 +991,11 @@ enum mkt_eth_capabilities {
|
|
|
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
|
|
|
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
|
|
|
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
|
|
|
@@ -791,7 +791,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
|
|
|
/* PATH BITS */
|
|
|
MTK_ETH_PATH_GMAC1_RGMII_BIT,
|
|
|
-@@ -975,14 +995,21 @@ enum mkt_eth_capabilities {
|
|
|
+@@ -983,14 +1003,21 @@ enum mkt_eth_capabilities {
|
|
|
MTK_ETH_PATH_GMAC1_SGMII_BIT,
|
|
|
MTK_ETH_PATH_GMAC2_RGMII_BIT,
|
|
|
MTK_ETH_PATH_GMAC2_SGMII_BIT,
|
|
|
@@ -813,7 +813,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
|
|
|
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
|
|
|
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
|
|
|
-@@ -1005,10 +1032,16 @@ enum mkt_eth_capabilities {
|
|
|
+@@ -1013,10 +1040,16 @@ enum mkt_eth_capabilities {
|
|
|
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
|
|
|
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
|
|
|
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
|
|
|
@@ -830,7 +830,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
|
|
|
/* Supported path present on SoCs */
|
|
|
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
|
|
|
-@@ -1016,8 +1049,13 @@ enum mkt_eth_capabilities {
|
|
|
+@@ -1024,8 +1057,13 @@ enum mkt_eth_capabilities {
|
|
|
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
|
|
|
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
|
|
|
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
|
|
|
@@ -844,7 +844,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
|
|
|
#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
|
|
|
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
|
|
|
-@@ -1025,7 +1063,12 @@ enum mkt_eth_capabilities {
|
|
|
+@@ -1033,7 +1071,12 @@ enum mkt_eth_capabilities {
|
|
|
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
|
|
|
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
|
|
|
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
|
|
|
@@ -857,7 +857,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
|
|
|
/* MUXes present on SoCs */
|
|
|
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
|
|
|
-@@ -1044,10 +1087,20 @@ enum mkt_eth_capabilities {
|
|
|
+@@ -1052,10 +1095,20 @@ enum mkt_eth_capabilities {
|
|
|
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
|
|
|
MTK_SHARED_SGMII)
|
|
|
|
|
|
@@ -878,7 +878,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
|
|
|
|
|
|
#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
|
|
|
-@@ -1079,8 +1132,12 @@ enum mkt_eth_capabilities {
|
|
|
+@@ -1087,8 +1140,12 @@ enum mkt_eth_capabilities {
|
|
|
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
|
|
|
MTK_RSTCTRL_PPE1 | MTK_SRAM)
|
|
|
|
|
|
@@ -893,7 +893,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
|
|
|
struct mtk_tx_dma_desc_info {
|
|
|
dma_addr_t addr;
|
|
|
-@@ -1325,6 +1382,9 @@ struct mtk_mac {
|
|
|
+@@ -1333,6 +1390,9 @@ struct mtk_mac {
|
|
|
struct device_node *of_node;
|
|
|
struct phylink *phylink;
|
|
|
struct phylink_config phylink_config;
|
|
|
@@ -903,7 +903,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
struct mtk_eth *hw;
|
|
|
struct mtk_hw_stats *hw_stats;
|
|
|
__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
|
|
|
-@@ -1448,6 +1508,19 @@ static inline u32 mtk_get_ib2_multicast_
|
|
|
+@@ -1456,6 +1516,19 @@ static inline u32 mtk_get_ib2_multicast_
|
|
|
return MTK_FOE_IB2_MULTICAST;
|
|
|
}
|
|
|
|
|
|
@@ -923,7 +923,7 @@ Signed-off-by: Daniel Golle <[email protected]>
|
|
|
/* read the hardware status register */
|
|
|
void mtk_stats_update_mac(struct mtk_mac *mac);
|
|
|
|
|
|
-@@ -1456,8 +1529,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
|
|
|
+@@ -1464,8 +1537,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
|
|
|
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
|
|
|
|
|
|
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
|