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-From 7b0c03ecc42fb223baf015877fee9d517c2c8af1 Mon Sep 17 00:00:00 2001
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-From: Christian Lamparter <[email protected]>
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-Date: Sat, 17 Nov 2018 17:17:21 +0100
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-Subject: dmaengine: dw-dmac: implement dma protection control setting
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-
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-This patch adds a new device-tree property that allows to
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-specify the dma protection control bits for the all of the
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-DMA controller's channel uniformly.
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-
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-Setting the "correct" bits can have a huge impact on the
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-PPC460EX and APM82181 that use this DMA engine in combination
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-with a DesignWare' SATA-II core (sata_dwc_460ex driver).
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-
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-In the OpenWrt Forum, the user takimata reported that:
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-|It seems your patch unleashed the full power of the SATA port.
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-|Where I was previously hitting a really hard limit at around
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-|82 MB/s for reading and 27 MB/s for writing, I am now getting this:
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-|
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-|root@OpenWrt:/mnt# time dd if=/dev/zero of=tempfile bs=1M count=1024
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-|1024+0 records in
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-|1024+0 records out
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-|real 0m 13.65s
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-|user 0m 0.01s
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-|sys 0m 11.89s
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-|
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-|root@OpenWrt:/mnt# time dd if=tempfile of=/dev/null bs=1M count=1024
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-|1024+0 records in
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-|1024+0 records out
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-|real 0m 8.41s
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-|user 0m 0.01s
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-|sys 0m 4.70s
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-|
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-|This means: 121 MB/s reading and 75 MB/s writing!
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-|
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-|The drive is a WD Green WD10EARX taken from an older MBL Single.
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-|I repeated the test a few times with even larger files to rule out
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-|any caching, I'm still seeing the same great performance. OpenWrt is
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-|now completely on par with the original MBL firmware's performance.
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-
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-Another user And.short reported:
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-|I can report that your fix worked! Boots up fine with two
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-|drives even with more partitions, and no more reboot on
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-|concurrent disk access!
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-
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-A closer look into the sata_dwc_460ex code revealed that
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-the driver did initally set the correct protection control
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-bits. However, this feature was lost when the sata_dwc_460ex
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-driver was converted to the generic DMA driver framework.
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-
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-BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/55
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-BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/50
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-Fixes: 8b3444852a2b ("sata_dwc_460ex: move to generic DMA driver")
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-Reviewed-by: Andy Shevchenko <[email protected]>
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-Signed-off-by: Christian Lamparter <[email protected]>
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-Signed-off-by: Vinod Koul <[email protected]>
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----
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-
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---- a/drivers/dma/dw/core.c
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-+++ b/drivers/dma/dw/core.c
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-@@ -160,12 +160,14 @@ static void dwc_initialize_chan_idma32(s
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-
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- static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
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- {
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-+ struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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- u32 cfghi = DWC_CFGH_FIFO_MODE;
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- u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
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- bool hs_polarity = dwc->dws.hs_polarity;
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-
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- cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
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- cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
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-+ cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
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-
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- /* Set polarity of handshake interface */
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- cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
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---- a/drivers/dma/dw/platform.c
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-+++ b/drivers/dma/dw/platform.c
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-@@ -162,6 +162,12 @@ dw_dma_parse_dt(struct platform_device *
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- pdata->multi_block[tmp] = 1;
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- }
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-
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-+ if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
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-+ if (tmp > CHAN_PROTCTL_MASK)
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-+ return NULL;
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-+ pdata->protctl = tmp;
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-+ }
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-+
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- return pdata;
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- }
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- #else
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---- a/drivers/dma/dw/regs.h
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-+++ b/drivers/dma/dw/regs.h
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-@@ -200,6 +200,10 @@ enum dw_dma_msize {
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- #define DWC_CFGH_FCMODE (1 << 0)
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- #define DWC_CFGH_FIFO_MODE (1 << 1)
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- #define DWC_CFGH_PROTCTL(x) ((x) << 2)
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-+#define DWC_CFGH_PROTCTL_DATA (0 << 2) /* data access - always set */
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-+#define DWC_CFGH_PROTCTL_PRIV (1 << 2) /* privileged -> AHB HPROT[1] */
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-+#define DWC_CFGH_PROTCTL_BUFFER (2 << 2) /* bufferable -> AHB HPROT[2] */
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-+#define DWC_CFGH_PROTCTL_CACHE (4 << 2) /* cacheable -> AHB HPROT[3] */
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- #define DWC_CFGH_DS_UPD_EN (1 << 5)
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- #define DWC_CFGH_SS_UPD_EN (1 << 6)
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- #define DWC_CFGH_SRC_PER(x) ((x) << 7)
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---- a/include/linux/platform_data/dma-dw.h
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-+++ b/include/linux/platform_data/dma-dw.h
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-@@ -49,6 +49,7 @@ struct dw_dma_slave {
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- * @data_width: Maximum data width supported by hardware per AHB master
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- * (in bytes, power of 2)
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- * @multi_block: Multi block transfers supported by hardware per channel.
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-+ * @protctl: Protection control signals setting per channel.
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- */
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- struct dw_dma_platform_data {
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- unsigned int nr_channels;
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-@@ -65,6 +66,11 @@ struct dw_dma_platform_data {
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- unsigned char nr_masters;
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- unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
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- unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
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-+#define CHAN_PROTCTL_PRIVILEGED BIT(0)
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-+#define CHAN_PROTCTL_BUFFERABLE BIT(1)
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-+#define CHAN_PROTCTL_CACHEABLE BIT(2)
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-+#define CHAN_PROTCTL_MASK GENMASK(2, 0)
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-+ unsigned char protctl;
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- };
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-
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- #endif /* _PLATFORM_DATA_DMA_DW_H */
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---- /dev/null
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-+++ b/include/dt-bindings/dma/dw-dmac.h
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-@@ -0,0 +1,14 @@
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-+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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-+
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-+#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__
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-+#define __DT_BINDINGS_DMA_DW_DMAC_H__
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-+
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-+/*
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-+ * Protection Control bits provide protection against illegal transactions.
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-+ * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
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-+ */
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-+#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */
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-+#define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */
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-+#define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */
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-+
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-+#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */
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