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@@ -199,6 +199,8 @@ static inline void mailbox_oam_rx_handler(void);
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static inline void mailbox_aal_rx_handler(void);
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static irqreturn_t mailbox_irq_handler(int, void *);
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static inline void mailbox_signal(unsigned int, int);
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+static void do_ppe_tasklet(unsigned long);
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+DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
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/*
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* QSB & HTU setting functions
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@@ -491,6 +493,9 @@ static void ppe_close(struct atm_vcc *vcc)
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break;
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}
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+ /* wait for incoming packets to be processed by upper layers */
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+ tasklet_unlock_wait(&g_dma_tasklet);
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+
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PPE_CLOSE_EXIT:
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return;
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}
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@@ -1039,14 +1044,25 @@ static inline void mailbox_aal_rx_handler(void)
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}
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}
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+static void do_ppe_tasklet(unsigned long data)
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+{
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+ *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
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+ mailbox_oam_rx_handler();
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+ mailbox_aal_rx_handler();
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+
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+ if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
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+ tasklet_schedule(&g_dma_tasklet);
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+ else
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+ enable_irq(PPE_MAILBOX_IGU1_INT);
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+}
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+
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static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
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{
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if ( !*MBOX_IGU1_ISR )
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return IRQ_HANDLED;
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- *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
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- mailbox_oam_rx_handler();
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- mailbox_aal_rx_handler();
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+ disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
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+ tasklet_schedule(&g_dma_tasklet);
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return IRQ_HANDLED;
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}
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