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@@ -0,0 +1,39 @@
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+From: Shiji Yang <[email protected]>
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+Date: Wed, 10 Jul 2024 12:18:52 +0800
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+Subject: [PATCH] mmc: mtk-sd: initialize the pad and tune registers
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+
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+Signed-off-by: Shiji Yang <[email protected]>
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+---
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+
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+--- a/drivers/mmc/host/mtk-sd.c
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++++ b/drivers/mmc/host/mtk-sd.c
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+@@ -75,8 +75,12 @@
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+ #define MSDC_PATCH_BIT 0xb0
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+ #define MSDC_PATCH_BIT1 0xb4
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+ #define MSDC_PATCH_BIT2 0xb8
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++#define MSDC_PAD_CTRL0 0xe0
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++#define MSDC_PAD_CTRL1 0xe4
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++#define MSDC_PAD_CTRL2 0xe8
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+ #define MSDC_PAD_TUNE 0xec
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+ #define MSDC_PAD_TUNE0 0xf0
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++#define MSDC_PAD_TUNE1 0xf4
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+ #define PAD_DS_TUNE 0x188
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+ #define PAD_CMD_TUNE 0x18c
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+ #define EMMC51_CFG0 0x204
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+@@ -1795,6 +1799,16 @@ static void msdc_init_hw(struct msdc_hos
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+ MSDC_PAD_TUNE_RXDLYSEL);
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+ }
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+
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++ /* Set pins drive strength */
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++ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
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++ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
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++ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
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++
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++ /* Set pad delay */
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++ writel(0x84101010, host->base + MSDC_PAD_TUNE);
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++ writel(0x10101010, host->base + MSDC_PAD_TUNE0);
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++ writel(0x10101010, host->base + MSDC_PAD_TUNE1);
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++
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+ if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
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+ sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
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+ sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
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