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@@ -0,0 +1,355 @@
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+From 3907f1ffc0ecf466d5c04aadc44c4b9203f3ec9a Mon Sep 17 00:00:00 2001
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+From: Heiner Kallweit <[email protected]>
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+Date: Thu, 1 Feb 2024 22:38:01 +0100
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+Subject: [PATCH] r8169: add support for RTL8126A
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+
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+This adds support for the RTL8126A found on Asus z790 Maximus Formula.
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+It was successfully tested w/o the firmware at 1000Mbps. Firmware file
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+has been provided by Realtek and submitted to linux-firmware.
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+2.5G and 5G modes are untested.
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+
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+Signed-off-by: Heiner Kallweit <[email protected]>
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+Signed-off-by: David S. Miller <[email protected]>
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+---
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+ drivers/net/ethernet/realtek/r8169.h | 1 +
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+ drivers/net/ethernet/realtek/r8169_main.c | 105 ++++++++++++++----
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+ .../net/ethernet/realtek/r8169_phy_config.c | 7 ++
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+ 3 files changed, 89 insertions(+), 24 deletions(-)
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+
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+--- a/drivers/net/ethernet/realtek/r8169.h
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++++ b/drivers/net/ethernet/realtek/r8169.h
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+@@ -68,6 +68,7 @@ enum mac_version {
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+ /* support for RTL_GIGA_MAC_VER_60 has been removed */
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+ RTL_GIGA_MAC_VER_61,
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+ RTL_GIGA_MAC_VER_63,
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++ RTL_GIGA_MAC_VER_65,
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+ RTL_GIGA_MAC_NONE
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+ };
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+
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+--- a/drivers/net/ethernet/realtek/r8169_main.c
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++++ b/drivers/net/ethernet/realtek/r8169_main.c
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+@@ -55,6 +55,7 @@
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+ #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
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+ #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
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+ #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
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++#define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
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+
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+ /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
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+ The RTL chips use a 64 element hash table based on the Ethernet CRC. */
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+@@ -140,6 +141,7 @@ static const struct {
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+ [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
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+ /* reserve 62 for CFG_METHOD_4 in the vendor driver */
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+ [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
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++ [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2},
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+ };
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+
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+ static const struct pci_device_id rtl8169_pci_tbl[] = {
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+@@ -162,6 +164,7 @@ static const struct pci_device_id rtl816
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+ { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
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+ { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
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+ { PCI_VDEVICE(REALTEK, 0x8125) },
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++ { PCI_VDEVICE(REALTEK, 0x8126) },
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+ { PCI_VDEVICE(REALTEK, 0x3000) },
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+ {}
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+ };
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+@@ -331,8 +334,12 @@ enum rtl8168_registers {
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+ };
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+
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+ enum rtl8125_registers {
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++ INT_CFG0_8125 = 0x34,
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++#define INT_CFG0_ENABLE_8125 BIT(0)
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++#define INT_CFG0_CLKREQEN BIT(3)
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+ IntrMask_8125 = 0x38,
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+ IntrStatus_8125 = 0x3c,
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++ INT_CFG1_8125 = 0x7a,
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+ TxPoll_8125 = 0x90,
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+ MAC0_BKP = 0x19e0,
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+ EEE_TXIDLE_TIMER_8125 = 0x6048,
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+@@ -1144,7 +1151,7 @@ static void rtl_writephy(struct rtl8169_
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+ case RTL_GIGA_MAC_VER_31:
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+ r8168dp_2_mdio_write(tp, location, val);
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+ break;
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+- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ r8168g_mdio_write(tp, location, val);
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+ break;
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+ default:
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+@@ -1159,7 +1166,7 @@ static int rtl_readphy(struct rtl8169_pr
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+ case RTL_GIGA_MAC_VER_28:
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+ case RTL_GIGA_MAC_VER_31:
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+ return r8168dp_2_mdio_read(tp, location);
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+- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ return r8168g_mdio_read(tp, location);
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+ default:
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+ return r8169_mdio_read(tp, location);
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+@@ -1368,7 +1375,7 @@ static void rtl_set_d3_pll_down(struct r
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+ case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
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+ case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
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+ case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
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+- case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
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+ if (enable)
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+ RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
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+ else
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+@@ -1535,7 +1542,7 @@ static void __rtl8169_set_wol(struct rtl
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+ break;
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+ case RTL_GIGA_MAC_VER_34:
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+ case RTL_GIGA_MAC_VER_37:
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+- case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
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+ if (wolopts)
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+ rtl_mod_config2(tp, 0, PME_SIGNAL);
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+ else
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+@@ -2122,6 +2129,9 @@ static enum mac_version rtl8169_get_mac_
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+ u16 val;
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+ enum mac_version ver;
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+ } mac_info[] = {
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++ /* 8126A family. */
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++ { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
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++
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+ /* 8125B family. */
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+ { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
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+
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+@@ -2392,6 +2402,7 @@ static void rtl_init_rxcfg(struct rtl816
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+ RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
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+ break;
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+ case RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_65:
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+ RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
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+ RX_PAUSE_SLOT_ON);
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+ break;
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+@@ -2578,7 +2589,7 @@ static void rtl_wait_txrx_fifo_empty(str
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+ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
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+ rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
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+ break;
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+- case RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65:
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+ RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
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+ rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
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+ rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
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+@@ -2822,7 +2833,7 @@ static void rtl_enable_exit_l1(struct rt
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+ case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
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+ rtl_eri_set_bits(tp, 0xd4, 0x0c00);
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+ break;
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+- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
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+ break;
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+ default:
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+@@ -2836,7 +2847,7 @@ static void rtl_disable_exit_l1(struct r
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+ case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
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+ rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
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+ break;
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+- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
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+ break;
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+ default:
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+@@ -2846,6 +2857,8 @@ static void rtl_disable_exit_l1(struct r
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+
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+ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
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+ {
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++ u8 val8;
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++
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+ if (tp->mac_version < RTL_GIGA_MAC_VER_32)
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+ return;
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+
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+@@ -2859,11 +2872,19 @@ static void rtl_hw_aspm_clkreq_enable(st
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+ return;
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+
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+ rtl_mod_config5(tp, 0, ASPM_en);
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+- rtl_mod_config2(tp, 0, ClkReqEn);
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++ switch (tp->mac_version) {
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++ case RTL_GIGA_MAC_VER_65:
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++ val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
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++ RTL_W8(tp, INT_CFG0_8125, val8);
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++ break;
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++ default:
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++ rtl_mod_config2(tp, 0, ClkReqEn);
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++ break;
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++ }
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+
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+ switch (tp->mac_version) {
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+ case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
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+- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
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+ /* reset ephy tx/rx disable timer */
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+ r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
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+ /* chip can trigger L1.2 */
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+@@ -2875,14 +2896,22 @@ static void rtl_hw_aspm_clkreq_enable(st
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+ } else {
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+ switch (tp->mac_version) {
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+ case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
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+- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
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+ r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
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+ break;
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+ default:
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+ break;
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+ }
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+
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+- rtl_mod_config2(tp, ClkReqEn, 0);
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++ switch (tp->mac_version) {
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++ case RTL_GIGA_MAC_VER_65:
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++ val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
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++ RTL_W8(tp, INT_CFG0_8125, val8);
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++ break;
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++ default:
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++ rtl_mod_config2(tp, ClkReqEn, 0);
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++ break;
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++ }
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+ rtl_mod_config5(tp, ASPM_en, 0);
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+ }
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+ }
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+@@ -3678,10 +3707,15 @@ static void rtl_hw_start_8125_common(str
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+ /* disable new tx descriptor format */
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+ r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
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+
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+- if (tp->mac_version == RTL_GIGA_MAC_VER_63)
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++ if (tp->mac_version == RTL_GIGA_MAC_VER_65)
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++ RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
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++
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++ if (tp->mac_version == RTL_GIGA_MAC_VER_65)
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++ r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
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++ else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
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+ r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
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+ else
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+- r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
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++ r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300);
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+
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+ if (tp->mac_version == RTL_GIGA_MAC_VER_63)
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+ r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
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+@@ -3694,6 +3728,10 @@ static void rtl_hw_start_8125_common(str
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+ r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
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+ r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
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+ r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
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++ if (tp->mac_version == RTL_GIGA_MAC_VER_65)
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++ r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
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++ else
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++ r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
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+ r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
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+ r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
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+ r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
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+@@ -3708,10 +3746,10 @@ static void rtl_hw_start_8125_common(str
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+
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+ rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
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+
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+- if (tp->mac_version == RTL_GIGA_MAC_VER_63)
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+- rtl8125b_config_eee_mac(tp);
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+- else
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++ if (tp->mac_version == RTL_GIGA_MAC_VER_61)
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+ rtl8125a_config_eee_mac(tp);
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++ else
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++ rtl8125b_config_eee_mac(tp);
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+
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+ rtl_disable_rxdvgate(tp);
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+ }
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+@@ -3755,6 +3793,12 @@ static void rtl_hw_start_8125b(struct rt
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+ rtl_hw_start_8125_common(tp);
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+ }
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+
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++static void rtl_hw_start_8126a(struct rtl8169_private *tp)
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++{
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++ rtl_set_def_aspm_entry_latency(tp);
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++ rtl_hw_start_8125_common(tp);
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++}
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++
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+ static void rtl_hw_config(struct rtl8169_private *tp)
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+ {
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+ static const rtl_generic_fct hw_configs[] = {
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+@@ -3797,6 +3841,7 @@ static void rtl_hw_config(struct rtl8169
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+ [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
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+ [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
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+ [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
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++ [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
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+ };
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+
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+ if (hw_configs[tp->mac_version])
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+@@ -3807,9 +3852,23 @@ static void rtl_hw_start_8125(struct rtl
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+ {
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+ int i;
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+
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++ RTL_W8(tp, INT_CFG0_8125, 0x00);
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++
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+ /* disable interrupt coalescing */
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+- for (i = 0xa00; i < 0xb00; i += 4)
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+- RTL_W32(tp, i, 0);
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++ switch (tp->mac_version) {
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++ case RTL_GIGA_MAC_VER_61:
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++ for (i = 0xa00; i < 0xb00; i += 4)
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++ RTL_W32(tp, i, 0);
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++ break;
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++ case RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_65:
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++ for (i = 0xa00; i < 0xa80; i += 4)
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++ RTL_W32(tp, i, 0);
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++ RTL_W16(tp, INT_CFG1_8125, 0x0000);
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++ break;
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++ default:
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++ break;
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++ }
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+
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+ rtl_hw_config(tp);
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+ }
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+@@ -3887,8 +3946,7 @@ static int rtl8169_change_mtu(struct net
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+ rtl_jumbo_config(tp);
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+
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+ switch (tp->mac_version) {
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+- case RTL_GIGA_MAC_VER_61:
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+- case RTL_GIGA_MAC_VER_63:
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++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
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+ rtl8125_set_eee_txidle_timer(tp);
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+ break;
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+ default:
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+@@ -4037,7 +4095,7 @@ static void rtl8169_cleanup(struct rtl81
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+ RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
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+ rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
|
|
|
+ break;
|
|
|
+- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
|
|
|
++ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
|
|
|
+ rtl_enable_rxdvgate(tp);
|
|
|
+ fsleep(2000);
|
|
|
+ break;
|
|
|
+@@ -4188,8 +4246,7 @@ static unsigned int rtl_quirk_packet_pad
|
|
|
+
|
|
|
+ switch (tp->mac_version) {
|
|
|
+ case RTL_GIGA_MAC_VER_34:
|
|
|
+- case RTL_GIGA_MAC_VER_61:
|
|
|
+- case RTL_GIGA_MAC_VER_63:
|
|
|
++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
|
|
|
+ padto = max_t(unsigned int, padto, ETH_ZLEN);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+@@ -5225,7 +5282,7 @@ static void rtl_hw_initialize(struct rtl
|
|
|
+ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
|
|
|
+ rtl_hw_init_8168g(tp);
|
|
|
+ break;
|
|
|
+- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
|
|
|
++ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
|
|
|
+ rtl_hw_init_8125(tp);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+--- a/drivers/net/ethernet/realtek/r8169_phy_config.c
|
|
|
++++ b/drivers/net/ethernet/realtek/r8169_phy_config.c
|
|
|
+@@ -1102,6 +1102,12 @@ static void rtl8125b_hw_phy_config(struc
|
|
|
+ rtl8125b_config_eee_phy(phydev);
|
|
|
+ }
|
|
|
+
|
|
|
++static void rtl8126a_hw_phy_config(struct rtl8169_private *tp,
|
|
|
++ struct phy_device *phydev)
|
|
|
++{
|
|
|
++ r8169_apply_firmware(tp);
|
|
|
++}
|
|
|
++
|
|
|
+ void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
|
|
|
+ enum mac_version ver)
|
|
|
+ {
|
|
|
+@@ -1152,6 +1158,7 @@ void r8169_hw_phy_config(struct rtl8169_
|
|
|
+ [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config,
|
|
|
+ [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
|
|
|
+ [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
|
|
|
++ [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,
|
|
|
+ };
|
|
|
+
|
|
|
+ if (phy_configs[ver])
|