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@@ -1,108 +0,0 @@
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-CNS3xxx SOCs have L310-compatible cache controller, so let's use it.
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-
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-With this patch benchmarking with 'gzip' shows that performance is
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-doubled, and I'm still able to boot full-fledged userland over NFS
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-(using PCIe NIC), so the support should be pretty robust.
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-
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-Signed-off-by: Anton Vorontsov <[email protected]>
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----
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-
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- arch/arm/mach-cns3xxx/cns3420vb.c | 2 +
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- arch/arm/mach-cns3xxx/core.c | 43 +++++++++++++++++++++++++++++++++++++
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- arch/arm/mach-cns3xxx/core.h | 6 +++++
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- arch/arm/mm/Kconfig | 2 +-
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- 4 files changed, 52 insertions(+), 1 deletions(-)
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-
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---- a/arch/arm/mach-cns3xxx/cns3420vb.c
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-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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-@@ -192,6 +192,8 @@ static struct platform_device *cns3420_p
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-
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- static void __init cns3420_init(void)
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- {
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-+ cns3xxx_l2x0_init();
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-+
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- platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
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-
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- cns3xxx_ahci_init();
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---- a/arch/arm/mach-cns3xxx/core.c
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-+++ b/arch/arm/mach-cns3xxx/core.c
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-@@ -16,6 +16,7 @@
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- #include <asm/mach/time.h>
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- #include <asm/mach/irq.h>
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- #include <asm/hardware/gic.h>
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-+#include <asm/hardware/cache-l2x0.h>
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- #include <mach/cns3xxx.h>
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- #include "core.h"
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-
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-@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(vo
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- struct sys_timer cns3xxx_timer = {
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- .init = cns3xxx_timer_init,
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- };
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-+
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-+#ifdef CONFIG_CACHE_L2X0
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-+
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-+void __init cns3xxx_l2x0_init(void)
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-+{
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-+ void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
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-+ u32 val;
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-+
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-+ if (WARN_ON(!base))
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-+ return;
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-+
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-+ /*
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-+ * Tag RAM Control register
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-+ *
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-+ * bit[10:8] - 1 cycle of write accesses latency
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-+ * bit[6:4] - 1 cycle of read accesses latency
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-+ * bit[3:0] - 1 cycle of setup latency
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-+ *
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-+ * 1 cycle of latency for setup, read and write accesses
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-+ */
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-+ val = readl(base + L2X0_TAG_LATENCY_CTRL);
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-+ val &= 0xfffff888;
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-+ writel(val, base + L2X0_TAG_LATENCY_CTRL);
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-+
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-+ /*
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-+ * Data RAM Control register
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-+ *
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-+ * bit[10:8] - 1 cycles of write accesses latency
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-+ * bit[6:4] - 1 cycles of read accesses latency
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-+ * bit[3:0] - 1 cycle of setup latency
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-+ *
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-+ * 1 cycle of latency for setup, read and write accesses
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-+ */
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-+ val = readl(base + L2X0_DATA_LATENCY_CTRL);
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-+ val &= 0xfffff888;
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-+ writel(val, base + L2X0_DATA_LATENCY_CTRL);
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-+
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-+ /* 32 KiB, 8-way, parity disable */
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-+ l2x0_init(base, 0x00540000, 0xfe000fff);
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-+}
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-+
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-+#endif /* CONFIG_CACHE_L2X0 */
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---- a/arch/arm/mach-cns3xxx/core.h
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-+++ b/arch/arm/mach-cns3xxx/core.h
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-@@ -13,6 +13,12 @@
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-
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- extern struct sys_timer cns3xxx_timer;
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-
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-+#ifdef CONFIG_CACHE_L2X0
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-+void __init cns3xxx_l2x0_init(void);
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-+#else
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-+static inline void cns3xxx_l2x0_init(void) {}
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-+#endif /* CONFIG_CACHE_L2X0 */
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-+
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- void __init cns3xxx_map_io(void);
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- void __init cns3xxx_init_irq(void);
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- void cns3xxx_power_off(void);
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---- a/arch/arm/mm/Kconfig
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-+++ b/arch/arm/mm/Kconfig
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-@@ -821,7 +821,7 @@ config CACHE_L2X0
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- depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
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- REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
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- ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
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-- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
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-+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
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- default y
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- select OUTER_CACHE
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- select OUTER_CACHE_SYNC
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