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@@ -0,0 +1,69 @@
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+From 9c9b415c50bc298ac61412dff856eae2f54889ee Mon Sep 17 00:00:00 2001
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+From: Ralf Baechle <[email protected]>
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+Date: Thu, 12 Sep 2013 13:47:32 +0200
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+Subject: [PATCH] MIPS: Reimplement get_cycles().
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+
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+This essentially reverts commit efb9ca08b5a2374b29938cdcab417ce4feb14b54
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+(kernel.org) / 58020a106879a8b372068741c81f0015c9b0b96dbv [[MIPS] Change
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+get_cycles to always return 0.]
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+
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+Most users of get_cycles() invoke it as a timing interface. That's why
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+in modern kernels it was never very much missed for. /dev/random however
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+uses get_cycles() in the how the jitter in the interrupt timing contains
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+some useful entropy.
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+
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+Signed-off-by: Ralf Baechle <[email protected]>
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+---
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+ arch/mips/include/asm/timex.h | 33 ++++++++++++++++++++++++++++++++-
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+ 1 file changed, 32 insertions(+), 1 deletion(-)
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+
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+--- a/arch/mips/include/asm/timex.h
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++++ b/arch/mips/include/asm/timex.h
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+@@ -10,6 +10,7 @@
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+
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+ #ifdef __KERNEL__
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+
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++#include <asm/cpu-features.h>
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+ #include <asm/mipsregs.h>
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+
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+ /*
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+@@ -33,9 +34,38 @@
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+
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+ typedef unsigned int cycles_t;
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+
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++/*
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++ * On R4000/R4400 before version 5.0 an erratum exists such that if the
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++ * cycle counter is read in the exact moment that it is matching the
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++ * compare register, no interrupt will be generated.
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++ *
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++ * There is a suggested workaround and also the erratum can't strike if
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++ * the compare interrupt isn't being used as the clock source device.
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++ * However for now the implementaton of this function doesn't get these
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++ * fine details right.
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++ */
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+ static inline cycles_t get_cycles(void)
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+ {
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+- return 0;
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++ switch (cpu_data[0].cputype) {
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++ case CPU_R4400PC:
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++ case CPU_R4400SC:
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++ case CPU_R4400MC:
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++ if ((read_c0_prid() & 0xff) >= 0x0050)
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++ return read_c0_count();
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++ break;
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++
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++ case CPU_R4000PC:
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++ case CPU_R4000SC:
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++ case CPU_R4000MC:
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++ break;
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++
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++ default:
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++ if (cpu_has_counter)
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++ return read_c0_count();
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++ break;
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++ }
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++
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++ return 0; /* no usable counter */
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+ }
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+
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+ #endif /* __KERNEL__ */
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