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@@ -0,0 +1,17 @@
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+Fix crash on cache flush with the MT_SMP variant
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+
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+Signed-off-by: Felix Fietkau <[email protected]>
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+
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+--- a/arch/mips/mm/c-r4k.c
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++++ b/arch/mips/mm/c-r4k.c
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+@@ -60,8 +60,10 @@ static inline void r4k_on_each_cpu(void
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+ * to restrict that call when a CM is not present because both
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+ * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops.
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+ */
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++#ifndef CONFIG_MIPS_MT_SMP
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+ if (!mips_cm_present())
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+ smp_call_function_many(&cpu_foreign_map, func, info, 1);
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++#endif
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+ func(info);
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+ preempt_enable();
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+ }
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