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@@ -31,6 +31,7 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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+
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cpu0: cpu@0 {
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compatible = "arm,cortex-a73";
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reg = <0x0>;
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@@ -82,18 +83,22 @@
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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+
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opp00 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <850000>;
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};
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+
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opp01 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <850000>;
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};
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+
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opp02 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <850000>;
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};
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+
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opp03 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <900000>;
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@@ -104,18 +109,22 @@
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cci_opp: opp_table_cci {
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compatible = "operating-points-v2";
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opp-shared;
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+
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opp00 {
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <850000>;
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};
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+
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opp01 {
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opp-hz = /bits/ 64 <660000000>;
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opp-microvolt = <850000>;
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};
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+
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opp02 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <850000>;
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};
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+
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opp03 {
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opp-hz = /bits/ 64 <1080000000>;
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opp-microvolt = <900000>;
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@@ -136,8 +145,8 @@
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};
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psci {
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- compatible = "arm,psci-0.2";
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- method = "smc";
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+ compatible = "arm,psci-0.2";
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+ method = "smc";
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};
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reg_1p8v: regulator-1p8v {
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@@ -226,12 +235,12 @@
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7988-pinctrl", "syscon";
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reg = <0 0x1001f000 0 0x1000>,
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- <0 0x11c10000 0 0x1000>,
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- <0 0x11d00000 0 0x1000>,
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- <0 0x11d20000 0 0x1000>,
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- <0 0x11e00000 0 0x1000>,
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- <0 0x11f00000 0 0x1000>,
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- <0 0x1000b000 0 0x1000>;
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+ <0 0x11c10000 0 0x1000>,
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+ <0 0x11d00000 0 0x1000>,
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+ <0 0x11d20000 0 0x1000>,
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+ <0 0x11e00000 0 0x1000>,
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+ <0 0x11f00000 0 0x1000>,
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+ <0 0x1000b000 0 0x1000>;
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reg-names = "gpio_base", "iocfg_tr_base",
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"iocfg_br_base", "iocfg_rb_base",
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"iocfg_lb_base", "iocfg_tl_base", "eint";
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@@ -955,12 +964,14 @@
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#address-cells = <2>;
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#size-cells = <2>;
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status = "disabled";
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+
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tphyu2port0: usb-phy@11c50000 {
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reg = <0 0x11c50000 0 0x700>;
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clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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+
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tphyu3port0: usb-phy@11c50700 {
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reg = <0 0x11c50700 0 0x900>;
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clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
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@@ -1036,18 +1047,23 @@
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lvts_calibration: calib@918 {
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reg = <0x918 0x28>;
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};
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+
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phy_calibration_p0: calib@940 {
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reg = <0x940 0x10>;
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};
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+
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phy_calibration_p1: calib@954 {
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reg = <0x954 0x10>;
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};
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+
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phy_calibration_p2: calib@968 {
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reg = <0x968 0x10>;
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};
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+
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phy_calibration_p3: calib@97c {
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reg = <0x97c 0x10>;
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};
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+
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cpufreq_calibration: calib@278 {
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reg = <0x278 0x1>;
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};
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@@ -1374,6 +1390,7 @@
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&lvts 0>;
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+
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trips {
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cpu_trip_crit: crit {
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temperature = <125000>;
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Rafał Miłecki