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@@ -1,24 +1,55 @@
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-From: George Moussalem <[email protected]>
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-Date: Fri, 28 Feb 2025 09:11:39 +0400
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-Subject: [PATCH v9 6/6] arm64: dts: qcom: ipq5018: Add tsens node
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-
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+From 450a80623e3b8bb5dae59e0d56046fc3d0a88f3b Mon Sep 17 00:00:00 2001
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From: Sricharan Ramabadhran <[email protected]>
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From: Sricharan Ramabadhran <[email protected]>
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+Date: Thu, 12 Jun 2025 10:46:14 +0400
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+Subject: arm64: dts: qcom: ipq5018: Add tsens node
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IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
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IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
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There is no RPM, so tsens has to be manually enabled. Adding the tsens
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There is no RPM, so tsens has to be manually enabled. Adding the tsens
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-and nvmem nodes and adding 4 thermal sensors (zones). With the
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-critical temperature being 120'C and action is to reboot.
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+and nvmem nodes and adding 4 thermal sensors (zones). The critical trip
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+temperature is set to 120'C with an action to reboot.
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+
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+In addition, adding a cooling device to the CPU thermal zone which uses
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+CPU frequency scaling.
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Reviewed-by: Dmitry Baryshkov <[email protected]>
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Reviewed-by: Dmitry Baryshkov <[email protected]>
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Signed-off-by: Sricharan Ramabadhran <[email protected]>
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Signed-off-by: Sricharan Ramabadhran <[email protected]>
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Signed-off-by: George Moussalem <[email protected]>
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Signed-off-by: George Moussalem <[email protected]>
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+Reviewed-by: Konrad Dybcio <[email protected]>
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+[bjorn: Added tsens-v1 fallback compatible, per binding]
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+Link: https://lore.kernel.org/r/[email protected]
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---
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---
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- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++
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- 1 file changed, 169 insertions(+)
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+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 178 ++++++++++++++++++++++++++++++++++
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+ 1 file changed, 178 insertions(+)
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+
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+(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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-@@ -182,6 +182,117 @@
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+@@ -9,6 +9,7 @@
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+ #include <dt-bindings/interrupt-controller/arm-gic.h>
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+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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++#include <dt-bindings/thermal/thermal.h>
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+
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+ / {
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+ interrupt-parent = <&intc>;
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+@@ -39,6 +40,7 @@
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+ next-level-cache = <&l2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ operating-points-v2 = <&cpu_opp_table>;
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++ #cooling-cells = <2>;
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+ };
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+
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+ cpu1: cpu@1 {
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+@@ -49,6 +51,7 @@
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+ next-level-cache = <&l2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ operating-points-v2 = <&cpu_opp_table>;
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++ #cooling-cells = <2>;
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+ };
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+
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+ l2_0: l2-cache {
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+@@ -182,6 +185,117 @@
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status = "disabled";
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status = "disabled";
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};
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};
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@@ -95,9 +126,9 @@ Signed-off-by: George Moussalem <[email protected]>
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+ };
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+ };
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+
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+
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+ tsens: thermal-sensor@4a9000 {
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+ tsens: thermal-sensor@4a9000 {
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-+ compatible = "qcom,ipq5018-tsens";
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-+ reg = <0x004a9000 0x1000>, /* TM */
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-+ <0x004a8000 0x1000>; /* SROT */
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++ compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
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++ reg = <0x004a9000 0x1000>,
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++ <0x004a8000 0x1000>;
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+
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+
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+ nvmem-cells = <&tsens_mode>,
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+ nvmem-cells = <&tsens_mode>,
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+ <&tsens_base1>,
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+ <&tsens_base1>,
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@@ -136,63 +167,69 @@ Signed-off-by: George Moussalem <[email protected]>
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tlmm: pinctrl@1000000 {
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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reg = <0x01000000 0x300000>;
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-@@ -630,6 +741,64 @@
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+@@ -630,6 +744,70 @@
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};
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};
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};
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};
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};
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};
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+
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+
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+ thermal-zones {
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+ thermal-zones {
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+ cpu-thermal {
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+ cpu-thermal {
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-+ polling-delay-passive = <0>;
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-+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 2>;
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+ thermal-sensors = <&tsens 2>;
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+
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+
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+ trips {
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+ trips {
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+ cpu-critical {
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+ cpu-critical {
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+ temperature = <120000>;
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+ temperature = <120000>;
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-+ hysteresis = <2>;
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++ hysteresis = <1000>;
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+ type = "critical";
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+ type = "critical";
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+ };
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+ };
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++
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++ cpu_alert: cpu-passive {
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++ temperature = <100000>;
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++ hysteresis = <1000>;
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++ type = "passive";
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++ };
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++ };
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++
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++ cooling-maps {
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++ map0 {
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++ trip = <&cpu_alert>;
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++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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++ };
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+ };
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+ };
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+ };
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+ };
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+
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+
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+ gephy-thermal {
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+ gephy-thermal {
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-+ polling-delay-passive = <0>;
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-+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 4>;
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+ thermal-sensors = <&tsens 4>;
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+
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+
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+ trips {
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+ trips {
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+ gephy-critical {
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+ gephy-critical {
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+ temperature = <120000>;
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+ temperature = <120000>;
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-+ hysteresis = <2>;
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++ hysteresis = <1000>;
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+ type = "critical";
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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+ };
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+ };
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+
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+
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+ top-glue-thermal {
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+ top-glue-thermal {
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-+ polling-delay-passive = <0>;
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-+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 3>;
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+ thermal-sensors = <&tsens 3>;
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+
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+
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+ trips {
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+ trips {
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-+ top_glue-critical {
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++ top-glue-critical {
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+ temperature = <120000>;
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+ temperature = <120000>;
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-+ hysteresis = <2>;
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++ hysteresis = <1000>;
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+ type = "critical";
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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+ };
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+ };
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+
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+
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+ ubi32-thermal {
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+ ubi32-thermal {
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-+ polling-delay-passive = <0>;
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-+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 1>;
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+ thermal-sensors = <&tsens 1>;
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+
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+
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+ trips {
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+ trips {
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+ ubi32-critical {
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+ ubi32-critical {
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+ temperature = <120000>;
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+ temperature = <120000>;
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-+ hysteresis = <2>;
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++ hysteresis = <1000>;
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+ type = "critical";
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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