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@@ -0,0 +1,310 @@
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+// SPDX-License-Identifier: GPL-2.0-only OR MIT
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+
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+/dts-v1/;
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/leds/common.h>
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+#include <dt-bindings/pinctrl/mt65xx.h>
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+
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+#include "mt7986a.dtsi"
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+
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+/ {
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+ compatible = "tplink,eap683-lr", "mediatek,mt7986a";
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+ model = "TP-Link EAP683-LR";
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+
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+ aliases {
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+ serial0 = &uart0;
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+ led-boot = &led_sys;
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+ led-running = &led_sys;
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+ led-upgrade = &led_sys;
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+ led-failsafe = &led_sys;
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+ };
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+
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+ /*
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+ * OEM U-Boot overwrites bootargs set in u-boot-env when running the mtkboardboot command
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+ *
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+ * with tp_boot_idx unset or set != 1:
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+ * console=ttyS0,115200n1 ubi.mtd=rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait loglevel=8 earlycon=uart8250,mmio32,0x11002000
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+ *
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+ * with tp_boot_idx set to 1:
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+ * console=ttyS0,115200n1 ubi.mtd=rootfs_1 root=/dev/ubiblock0_0 rootfstype=squashfs rootwait loglevel=8 earlycon=uart8250,mmio32,0x11002000
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+ */
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+
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+ chosen {
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+ bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@40000000 {
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+ reg = <0 0x40000000 0 0x20000000>;
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+ device_type = "memory";
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+ };
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+
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+ gpio-export {
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+ compatible = "gpio-export";
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+
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+ cc2652_backdoor {
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+ gpio-export,name = "cc2652_backdoor";
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+ gpio-export,output = <1>;
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+ gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ cc2652_reset {
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+ gpio-export,name = "cc2652_reset";
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+ gpio-export,output = <1>;
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+ gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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+ keys {
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+ compatible = "gpio-keys";
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+
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+ key-restart {
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+ label = "Reset";
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+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_RESTART>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led_sys: led-0 {
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+ function = LED_FUNCTION_STATUS;
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+ color = <LED_COLOR_ID_BLUE>;
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+ gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+};
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+
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+&crypto {
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+ status = "okay";
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+};
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+
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+ð {
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+ status = "okay";
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+
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+ mac@1 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <1>;
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+ phy-handle = <&phy5>;
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+ phy-mode = "2500base-x";
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+ };
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+
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+ mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reset-gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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+ reset-delay-us = <600>;
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+ reset-post-delay-us = <20000>;
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+
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+ phy5: ethernet-phy@5 {
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+ compatible = "maxlinear,gpy211", "ethernet-phy-ieee802.3-c45";
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+ reg = <5>;
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+ phy-mode = "2500base-x";
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+ };
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+ };
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+};
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+
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+&pcie {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie_pins>;
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+ status = "okay";
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+};
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+
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+&pcie_phy {
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+ status = "okay";
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+};
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+
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+&pio {
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+ pcie_pins: pcie-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
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+ };
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+ };
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+
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+ spi_flash_pins: spi-flash-pins-33-to-38 {
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+ mux {
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+ function = "spi";
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+ groups = "spi0", "spi0_wp_hold";
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+ };
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+ conf-pu {
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+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ mediatek,pull-up-adv = <MTK_PUPD_SET_R1R0_11>;
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+ };
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+ conf-pd {
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+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ mediatek,pull-down-adv = <MTK_PUPD_SET_R1R0_11>;
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+ };
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+ };
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+
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+ uart2_pins: uart2-pins {
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+ mux {
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+ function = "uart";
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+ groups = "uart2_0_rx_tx", "uart2_0_cts_rts";
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+ };
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+ };
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+
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+ wf_2g_5g_pins: wf_2g_5g-pins {
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+ mux {
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+ function = "wifi";
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+ groups = "wf_2g", "wf_5g";
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+ };
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+ conf {
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+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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+ "WF1_TOP_CLK", "WF1_TOP_DATA";
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+ drive-strength = <MTK_DRIVE_4mA>;
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+ };
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+ };
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+
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+ wf_dbdc_pins: wf-dbdc-pins {
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+ mux {
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+ function = "wifi";
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+ groups = "wf_dbdc";
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+ };
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+ conf {
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+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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+ "WF1_TOP_CLK", "WF1_TOP_DATA";
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+ drive-strength = <MTK_DRIVE_4mA>;
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+ };
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+ };
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+};
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+
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+&spi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi_flash_pins>;
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <52000000>;
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+ spi-rx-bus-width = <4>;
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+ spi-tx-bus-width = <4>;
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+ mediatek,nmbm;
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+ mediatek,bmt-max-ratio = <1>;
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+ mediatek,bmt-max-reserved-blocks = <64>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ reg = <0x0 0x100000>;
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+ label = "BL2";
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+ read-only;
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+ };
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+
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+ partition@100000 {
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+ reg = <0x100000 0x100000>;
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+ label = "boot-config";
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+ read-only;
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+ };
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+
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+ partition@200000 {
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+ reg = <0x200000 0x100000>;
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+ label = "boot-config1";
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+ read-only;
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+ };
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+
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+ partition@300000 {
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+ compatible = "u-boot,env";
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+ reg = <0x300000 0x100000>;
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+ label = "u-boot-env";
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+ };
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+
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+ partition@400000 {
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+ reg = <0x400000 0x200000>;
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+ label = "FIP0";
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+ read-only;
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+ };
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+
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+ partition@600000 {
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+ reg = <0x600000 0x200000>;
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+ label = "FIP1";
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+ read-only;
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+ };
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+
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+ partition@800000 {
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+ reg = <0x800000 0x100000>;
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+ label = "oops";
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+ };
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+
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+ partition@900000 {
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+ reg = <0x900000 0x2680000>;
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+ label = "ubi";
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+ };
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+
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+ partition@2f80000 {
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+ reg = <0x2f80000 0x2680000>;
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+ label = "ubi1";
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+ read-only;
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+ };
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+
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+ partition@5600000 {
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+ reg = <0x5600000 0x800000>;
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+ label = "factory";
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+ read-only;
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+ };
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+
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+ partition@5e00000 {
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+ reg = <0x5e00000 0xc00000>;
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+ label = "runtime_data";
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+ read-only;
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+ };
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+
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+ partition@6a00000 {
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+ reg = <0x6a00000 0x800000>;
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+ label = "backup_data";
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+ read-only;
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+ };
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+
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+ partition@7200000 {
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+ reg = <0x7200000 0x600000>;
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+ label = "runtime_backup";
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+ read-only;
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+ };
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+ };
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+ };
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+};
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+
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+&trng {
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+ status = "okay";
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart2_pins>;
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+ status = "okay";
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+};
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+
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+&watchdog {
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+ status = "okay";
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+};
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+
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+&wifi {
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+ pinctrl-names = "default", "dbdc";
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+ pinctrl-0 = <&wf_2g_5g_pins>;
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+ pinctrl-1 = <&wf_dbdc_pins>;
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+ status = "okay";
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+};
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