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@@ -0,0 +1,659 @@
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+From 3d6098a662b7ff5b80c4b75c54fcd1b2baf9f150 Mon Sep 17 00:00:00 2001
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+From: Linus Walleij <[email protected]>
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+Date: Mon, 24 Apr 2023 09:38:28 +0200
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+Subject: [PATCH 3/5] arm: dts: Import device tree for Broadcom Northstar
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+MIME-Version: 1.0
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+Content-Type: text/plain; charset=UTF-8
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+Content-Transfer-Encoding: 8bit
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+
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+This brings in the main SoC device tree used by the
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+Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
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+This is taken from the v6.3 Linux kernel.
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+
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+Cc: Rafał Miłecki <[email protected]>
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+Signed-off-by: Linus Walleij <[email protected]>
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+---
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+ arch/arm/dts/bcm5301x.dtsi | 581 ++++++++++++++++++++++++++++
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+ include/dt-bindings/clock/bcm-nsp.h | 51 +++
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+ 2 files changed, 632 insertions(+)
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+ create mode 100644 arch/arm/dts/bcm5301x.dtsi
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+ create mode 100644 include/dt-bindings/clock/bcm-nsp.h
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+
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+--- /dev/null
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++++ b/arch/arm/dts/bcm5301x.dtsi
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+@@ -0,0 +1,581 @@
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++/*
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++ * Broadcom BCM470X / BCM5301X ARM platform code.
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++ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
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++ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
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++ *
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++ * Copyright 2013-2014 Hauke Mehrtens <[email protected]>
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++ *
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++ * Licensed under the GNU/GPL. See COPYING for details.
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++ */
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++
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++#include <dt-bindings/clock/bcm-nsp.h>
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++#include <dt-bindings/gpio/gpio.h>
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++#include <dt-bindings/input/input.h>
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++#include <dt-bindings/interrupt-controller/irq.h>
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++#include <dt-bindings/interrupt-controller/arm-gic.h>
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++
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++/ {
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ interrupt-parent = <&gic>;
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++
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++ chipcommon-a-bus@18000000 {
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++ compatible = "simple-bus";
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++ ranges = <0x00000000 0x18000000 0x00001000>;
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++
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++ uart0: serial@300 {
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++ compatible = "ns16550";
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++ reg = <0x0300 0x100>;
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++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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++ clocks = <&iprocslow>;
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++ status = "disabled";
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++ };
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++
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++ uart1: serial@400 {
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++ compatible = "ns16550";
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++ reg = <0x0400 0x100>;
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++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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++ clocks = <&iprocslow>;
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++ pinctrl-names = "default";
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++ pinctrl-0 = <&pinmux_uart1>;
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++ status = "disabled";
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++ };
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++ };
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++
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++ mpcore-bus@19000000 {
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++ compatible = "simple-bus";
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++ ranges = <0x00000000 0x19000000 0x00023000>;
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++
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++ a9pll: arm_clk@0 {
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++ #clock-cells = <0>;
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++ compatible = "brcm,nsp-armpll";
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++ clocks = <&osc>;
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++ reg = <0x00000 0x1000>;
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++ };
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++
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++ scu@20000 {
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++ compatible = "arm,cortex-a9-scu";
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++ reg = <0x20000 0x100>;
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++ };
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++
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++ timer@20200 {
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++ compatible = "arm,cortex-a9-global-timer";
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++ reg = <0x20200 0x100>;
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++ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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++ clocks = <&periph_clk>;
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++ };
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++
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++ timer@20600 {
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++ compatible = "arm,cortex-a9-twd-timer";
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++ reg = <0x20600 0x20>;
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++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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++ IRQ_TYPE_EDGE_RISING)>;
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++ clocks = <&periph_clk>;
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++ };
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++
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++ watchdog@20620 {
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++ compatible = "arm,cortex-a9-twd-wdt";
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++ reg = <0x20620 0x20>;
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++ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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++ IRQ_TYPE_EDGE_RISING)>;
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++ clocks = <&periph_clk>;
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++ };
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++
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++ gic: interrupt-controller@21000 {
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++ compatible = "arm,cortex-a9-gic";
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++ #interrupt-cells = <3>;
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++ #address-cells = <0>;
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++ interrupt-controller;
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++ reg = <0x21000 0x1000>,
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++ <0x20100 0x100>;
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++ };
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++
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++ L2: cache-controller@22000 {
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++ compatible = "arm,pl310-cache";
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++ reg = <0x22000 0x1000>;
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++ cache-unified;
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++ arm,shared-override;
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++ prefetch-data = <1>;
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++ prefetch-instr = <1>;
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++ cache-level = <2>;
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++ };
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++ };
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++
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++ pmu {
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++ compatible = "arm,cortex-a9-pmu";
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++ interrupts =
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++ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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++ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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++ };
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++
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++ clocks {
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ ranges;
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++
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++ osc: oscillator {
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++ #clock-cells = <0>;
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++ compatible = "fixed-clock";
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++ clock-frequency = <25000000>;
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++ };
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++
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++ iprocmed: iprocmed {
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++ #clock-cells = <0>;
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++ compatible = "fixed-factor-clock";
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++ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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++ clock-div = <2>;
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++ clock-mult = <1>;
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++ };
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++
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++ iprocslow: iprocslow {
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++ #clock-cells = <0>;
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++ compatible = "fixed-factor-clock";
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++ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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++ clock-div = <4>;
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++ clock-mult = <1>;
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++ };
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++
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++ periph_clk: periph_clk {
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++ #clock-cells = <0>;
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++ compatible = "fixed-factor-clock";
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++ clocks = <&a9pll>;
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++ clock-div = <2>;
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++ clock-mult = <1>;
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++ };
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++ };
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++
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++ axi@18000000 {
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++ compatible = "brcm,bus-axi";
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++ reg = <0x18000000 0x1000>;
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++ ranges = <0x00000000 0x18000000 0x00100000>;
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++
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++ #interrupt-cells = <1>;
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++ interrupt-map-mask = <0x000fffff 0xffff>;
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++ interrupt-map =
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++ /* ChipCommon */
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++ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* Switch Register Access Block */
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++ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* PCIe Controller 0 */
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++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* PCIe Controller 1 */
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++ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* PCIe Controller 2 */
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++ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* USB 2.0 Controller */
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++ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* USB 3.0 Controller */
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++ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* Ethernet Controller 0 */
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++ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* Ethernet Controller 1 */
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++ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* Ethernet Controller 2 */
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++ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* Ethernet Controller 3 */
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++ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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++
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++ /* NAND Controller */
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++ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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++ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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++
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++ chipcommon: chipcommon@0 {
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++ reg = <0x00000000 0x1000>;
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++
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++ gpio-controller;
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++ #gpio-cells = <2>;
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++ interrupt-controller;
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++ #interrupt-cells = <2>;
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++ };
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++
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++ pcie0: pcie@12000 {
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++ reg = <0x00012000 0x1000>;
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++ };
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++
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++ pcie1: pcie@13000 {
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++ reg = <0x00013000 0x1000>;
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++ };
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++
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++ pcie2: pcie@14000 {
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++ reg = <0x00014000 0x1000>;
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++ };
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++
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++ usb2: usb2@21000 {
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++ reg = <0x00021000 0x1000>;
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++
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ ranges;
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++
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++ interrupt-parent = <&gic>;
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++
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++ ehci: usb@21000 {
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++ #usb-cells = <0>;
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++
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++ compatible = "generic-ehci";
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++ reg = <0x00021000 0x1000>;
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++ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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++ phys = <&usb2_phy>;
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++
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ ehci_port1: port@1 {
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++ reg = <1>;
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++ #trigger-source-cells = <0>;
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++ };
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++
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++ ehci_port2: port@2 {
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++ reg = <2>;
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++ #trigger-source-cells = <0>;
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++ };
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++ };
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++
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++ ohci: usb@22000 {
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++ #usb-cells = <0>;
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++
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++ compatible = "generic-ohci";
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++ reg = <0x00022000 0x1000>;
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++ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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++
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ ohci_port1: port@1 {
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++ reg = <1>;
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++ #trigger-source-cells = <0>;
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++ };
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++
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++ ohci_port2: port@2 {
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++ reg = <2>;
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++ #trigger-source-cells = <0>;
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++ };
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++ };
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++ };
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++
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++ usb3: usb3@23000 {
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++ reg = <0x00023000 0x1000>;
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++
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ ranges;
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++
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++ interrupt-parent = <&gic>;
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++
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++ xhci: usb@23000 {
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++ #usb-cells = <0>;
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++
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++ compatible = "generic-xhci";
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++ reg = <0x00023000 0x1000>;
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++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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++ phys = <&usb3_phy>;
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++ phy-names = "usb";
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++
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ xhci_port1: port@1 {
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++ reg = <1>;
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++ #trigger-source-cells = <0>;
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++ };
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++ };
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++ };
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++
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++ gmac0: ethernet@24000 {
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++ reg = <0x24000 0x800>;
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++ };
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++
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++ gmac1: ethernet@25000 {
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++ reg = <0x25000 0x800>;
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++ };
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++
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++ gmac2: ethernet@26000 {
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++ reg = <0x26000 0x800>;
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++ };
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++
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++ gmac3: ethernet@27000 {
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++ reg = <0x27000 0x800>;
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++ };
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++ };
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++
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++ pwm: pwm@18002000 {
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++ compatible = "brcm,iproc-pwm";
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++ reg = <0x18002000 0x28>;
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++ clocks = <&osc>;
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++ #pwm-cells = <3>;
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++ status = "disabled";
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++ };
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++
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++ mdio: mdio@18003000 {
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++ compatible = "brcm,iproc-mdio";
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++ reg = <0x18003000 0x8>;
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++ #size-cells = <0>;
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|
|
++ #address-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ mdio-mux@18003000 {
|
|
|
++ compatible = "mdio-mux-mmioreg", "mdio-mux";
|
|
|
++ mdio-parent-bus = <&mdio>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ reg = <0x18003000 0x4>;
|
|
|
++ mux-mask = <0x200>;
|
|
|
++
|
|
|
++ mdio@0 {
|
|
|
++ reg = <0x0>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ usb3_phy: usb3-phy@10 {
|
|
|
++ compatible = "brcm,ns-ax-usb3-phy";
|
|
|
++ reg = <0x10>;
|
|
|
++ usb3-dmp-syscon = <&usb3_dmp>;
|
|
|
++ #phy-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ usb3_dmp: syscon@18105000 {
|
|
|
++ reg = <0x18105000 0x1000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ uart2: serial@18008000 {
|
|
|
++ compatible = "ns16550a";
|
|
|
++ reg = <0x18008000 0x20>;
|
|
|
++ clocks = <&iprocslow>;
|
|
|
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c0: i2c@18009000 {
|
|
|
++ compatible = "brcm,iproc-i2c";
|
|
|
++ reg = <0x18009000 0x50>;
|
|
|
++ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ clock-frequency = <100000>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ dmu-bus@1800c000 {
|
|
|
++ compatible = "simple-bus";
|
|
|
++ ranges = <0 0x1800c000 0x1000>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ cru-bus@100 {
|
|
|
++ compatible = "brcm,ns-cru", "simple-mfd";
|
|
|
++ reg = <0x100 0x1a4>;
|
|
|
++ ranges;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ lcpll0: clock-controller@100 {
|
|
|
++ #clock-cells = <1>;
|
|
|
++ compatible = "brcm,nsp-lcpll0";
|
|
|
++ reg = <0x100 0x14>;
|
|
|
++ clocks = <&osc>;
|
|
|
++ clock-output-names = "lcpll0", "pcie_phy",
|
|
|
++ "sdio", "ddr_phy";
|
|
|
++ };
|
|
|
++
|
|
|
++ genpll: clock-controller@140 {
|
|
|
++ #clock-cells = <1>;
|
|
|
++ compatible = "brcm,nsp-genpll";
|
|
|
++ reg = <0x140 0x24>;
|
|
|
++ clocks = <&osc>;
|
|
|
++ clock-output-names = "genpll", "phy",
|
|
|
++ "ethernetclk",
|
|
|
++ "usbclk", "iprocfast",
|
|
|
++ "sata1", "sata2";
|
|
|
++ };
|
|
|
++
|
|
|
++ usb2_phy: phy@164 {
|
|
|
++ compatible = "brcm,ns-usb2-phy";
|
|
|
++ reg = <0x164 0x4>;
|
|
|
++ brcm,syscon-clkset = <&cru_clkset>;
|
|
|
++ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
|
|
|
++ clock-names = "phy-ref-clk";
|
|
|
++ #phy-cells = <0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ cru_clkset: syscon@180 {
|
|
|
++ compatible = "brcm,cru-clkset", "syscon";
|
|
|
++ reg = <0x180 0x4>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pinctrl: pinctrl@1c0 {
|
|
|
++ compatible = "brcm,bcm4708-pinmux";
|
|
|
++ reg = <0x1c0 0x24>;
|
|
|
++ reg-names = "cru_gpio_control";
|
|
|
++
|
|
|
++ spi-pins {
|
|
|
++ groups = "spi_grp";
|
|
|
++ function = "spi";
|
|
|
++ };
|
|
|
++
|
|
|
++ pinmux_i2c: i2c-pins {
|
|
|
++ groups = "i2c_grp";
|
|
|
++ function = "i2c";
|
|
|
++ };
|
|
|
++
|
|
|
++ pinmux_pwm: pwm-pins {
|
|
|
++ groups = "pwm0_grp", "pwm1_grp",
|
|
|
++ "pwm2_grp", "pwm3_grp";
|
|
|
++ function = "pwm";
|
|
|
++ };
|
|
|
++
|
|
|
++ pinmux_uart1: uart1-pins {
|
|
|
++ groups = "uart1_grp";
|
|
|
++ function = "uart1";
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ thermal: thermal@2c0 {
|
|
|
++ compatible = "brcm,ns-thermal";
|
|
|
++ reg = <0x2c0 0x10>;
|
|
|
++ #thermal-sensor-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ srab: ethernet-switch@18007000 {
|
|
|
++ compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
|
|
|
++ reg = <0x18007000 0x1000>;
|
|
|
++
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ /* ports are defined in board DTS */
|
|
|
++ ports {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ rng: rng@18004000 {
|
|
|
++ compatible = "brcm,bcm5301x-rng";
|
|
|
++ reg = <0x18004000 0x14>;
|
|
|
++ };
|
|
|
++
|
|
|
++ nand_controller: nand-controller@18028000 {
|
|
|
++ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
|
|
|
++ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
|
|
|
++ reg-names = "nand", "iproc-idm", "iproc-ext";
|
|
|
++ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
++
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ brcm,nand-has-wp;
|
|
|
++ };
|
|
|
++
|
|
|
++ spi@18029200 {
|
|
|
++ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
|
|
|
++ reg = <0x18029200 0x184>,
|
|
|
++ <0x18029000 0x124>,
|
|
|
++ <0x1811b408 0x004>,
|
|
|
++ <0x180293a0 0x01c>;
|
|
|
++ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
|
|
|
++ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
++ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
++ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
++ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
++ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
++ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
++ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
++ interrupt-names = "mspi_done",
|
|
|
++ "mspi_halted",
|
|
|
++ "spi_lr_fullness_reached",
|
|
|
++ "spi_lr_session_aborted",
|
|
|
++ "spi_lr_impatient",
|
|
|
++ "spi_lr_session_done",
|
|
|
++ "spi_lr_overread";
|
|
|
++ clocks = <&iprocmed>;
|
|
|
++ clock-names = "iprocmed";
|
|
|
++ num-cs = <2>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ spi_nor: flash@0 {
|
|
|
++ compatible = "jedec,spi-nor";
|
|
|
++ reg = <0>;
|
|
|
++ spi-max-frequency = <20000000>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ partitions {
|
|
|
++ compatible = "brcm,bcm947xx-cfe-partitions";
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ thermal-zones {
|
|
|
++ cpu_thermal: cpu-thermal {
|
|
|
++ polling-delay-passive = <0>;
|
|
|
++ polling-delay = <1000>;
|
|
|
++ coefficients = <(-556) 418000>;
|
|
|
++ thermal-sensors = <&thermal>;
|
|
|
++
|
|
|
++ trips {
|
|
|
++ cpu-crit {
|
|
|
++ temperature = <125000>;
|
|
|
++ hysteresis = <0>;
|
|
|
++ type = "critical";
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ cooling-maps {
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++};
|
|
|
+--- /dev/null
|
|
|
++++ b/include/dt-bindings/clock/bcm-nsp.h
|
|
|
+@@ -0,0 +1,51 @@
|
|
|
++/*
|
|
|
++ * BSD LICENSE
|
|
|
++ *
|
|
|
++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
|
|
|
++ *
|
|
|
++ * Redistribution and use in source and binary forms, with or without
|
|
|
++ * modification, are permitted provided that the following conditions
|
|
|
++ * are met:
|
|
|
++ *
|
|
|
++ * * Redistributions of source code must retain the above copyright
|
|
|
++ * notice, this list of conditions and the following disclaimer.
|
|
|
++ * * Redistributions in binary form must reproduce the above copyright
|
|
|
++ * notice, this list of conditions and the following disclaimer in
|
|
|
++ * the documentation and/or other materials provided with the
|
|
|
++ * distribution.
|
|
|
++ * * Neither the name of Broadcom Corporation nor the names of its
|
|
|
++ * contributors may be used to endorse or promote products derived
|
|
|
++ * from this software without specific prior written permission.
|
|
|
++ *
|
|
|
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
++ */
|
|
|
++
|
|
|
++#ifndef _CLOCK_BCM_NSP_H
|
|
|
++#define _CLOCK_BCM_NSP_H
|
|
|
++
|
|
|
++/* GENPLL clock channel ID */
|
|
|
++#define BCM_NSP_GENPLL 0
|
|
|
++#define BCM_NSP_GENPLL_PHY_CLK 1
|
|
|
++#define BCM_NSP_GENPLL_ENET_SW_CLK 2
|
|
|
++#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
|
|
|
++#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
|
|
|
++#define BCM_NSP_GENPLL_SATA1_CLK 5
|
|
|
++#define BCM_NSP_GENPLL_SATA2_CLK 6
|
|
|
++
|
|
|
++/* LCPLL0 clock channel ID */
|
|
|
++#define BCM_NSP_LCPLL0 0
|
|
|
++#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
|
|
|
++#define BCM_NSP_LCPLL0_SDIO_CLK 2
|
|
|
++#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
|
|
|
++
|
|
|
++#endif /* _CLOCK_BCM_NSP_H */
|
Linus Walleij