kernel: import accepted MediaTek Ethernet patches

Import some accepted and pending upstream patches for mtk_eth_soc,
replacing some semantically equivalent local patches and fixing issues
when operating the PCS in 1G SGMII mode.

Signed-off-by: Daniel Golle <[email protected]>

target/linux/generic/backport-5.15/733-v6.2-01-net-ethernet-mtk_eth_soc-Avoid-truncating-allocation.patch

@@ -0,0 +1,60 @@
+From f3eceaed9edd7c0e0d9fb057613131f92973626f Mon Sep 17 00:00:00 2001
+From: Kees Cook <[email protected]>
+Date: Fri, 27 Jan 2023 14:38:54 -0800
+Subject: [PATCH] net: ethernet: mtk_eth_soc: Avoid truncating allocation
+
+There doesn't appear to be a reason to truncate the allocation used for
+flow_info, so do a full allocation and remove the unused empty struct.
+GCC does not like having a reference to an object that has been
+partially allocated, as bounds checking may become impossible when
+such an object is passed to other code. Seen with GCC 13:
+
+../drivers/net/ethernet/mediatek/mtk_ppe.c: In function 'mtk_foe_entry_commit_subflow':
+../drivers/net/ethernet/mediatek/mtk_ppe.c:623:18: warning: array subscript 'struct mtk_flow_entry[0]' is partly outside array bounds of 'unsigned char[48]' [-Warray-bounds=]
+  623 |         flow_info->l2_data.base_flow = entry;
+      |                  ^~
+
+Cc: Felix Fietkau <[email protected]>
+Cc: John Crispin <[email protected]>
+Cc: Sean Wang <[email protected]>
+Cc: Mark Lee <[email protected]>
+Cc: Lorenzo Bianconi <[email protected]>
+Cc: "David S. Miller" <[email protected]>
+Cc: Eric Dumazet <[email protected]>
+Cc: Jakub Kicinski <[email protected]>
+Cc: Paolo Abeni <[email protected]>
+Cc: Matthias Brugger <[email protected]>
+Cc: [email protected]
+Cc: [email protected]
+Cc: [email protected]
+Signed-off-by: Kees Cook <[email protected]>
+Reviewed-by: Simon Horman <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Paolo Abeni <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_ppe.c | 3 +--
+ drivers/net/ethernet/mediatek/mtk_ppe.h | 1 -
+ 2 files changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -601,8 +601,7 @@ mtk_foe_entry_commit_subflow(struct mtk_
+ 	u32 ib1_mask = mtk_get_ib1_pkt_type_mask(ppe->eth) | MTK_FOE_IB1_UDP;
+ 	int type;
+ 
+-	flow_info = kzalloc(offsetof(struct mtk_flow_entry, l2_data.end),
+-			    GFP_ATOMIC);
++	flow_info = kzalloc(sizeof(*flow_info), GFP_ATOMIC);
+ 	if (!flow_info)
+ 		return;
+ 
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -277,7 +277,6 @@ struct mtk_flow_entry {
+ 		struct {
+ 			struct mtk_flow_entry *base_flow;
+ 			struct hlist_node list;
+-			struct {} end;
+ 		} l2_data;
+ 	};
+ 	struct rhash_head node;

target/linux/generic/backport-5.15/733-v6.2-02-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch

@@ -0,0 +1,126 @@
+From 7ff82416de8295c61423ef6fd75f052d3837d2f7 Mon Sep 17 00:00:00 2001
+From: Alexander Couzens <[email protected]>
+Date: Wed, 1 Feb 2023 19:23:29 +0100
+Subject: [PATCH] net: mediatek: sgmii: ensure the SGMII PHY is powered down on
+ configuration
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The code expect the PHY to be in power down which is only true after reset.
+Allow changes of the SGMII parameters more than once.
+
+Only power down when reconfiguring to avoid bouncing the link when there's
+no reason to - based on code from Russell King.
+
+There are cases when the SGMII_PHYA_PWD register contains 0x9 which
+prevents SGMII from working. The SGMII still shows link but no traffic
+can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
+taken from a good working state of the SGMII interface.
+
+Fixes: 42c03844e93d ("net-next: mediatek: add support for MediaTek MT7622 SoC")
+Suggested-by: Russell King (Oracle) <[email protected]>
+Signed-off-by: Alexander Couzens <[email protected]>
+[ bmork: rebased and squashed into one patch ]
+Reviewed-by: Russell King (Oracle) <[email protected]>
+Signed-off-by: Bjørn Mork <[email protected]>
+Acked-by: Daniel Golle <[email protected]>
+Tested-by: Daniel Golle <[email protected]>
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  2 ++
+ drivers/net/ethernet/mediatek/mtk_sgmii.c   | 39 +++++++++++++++------
+ 2 files changed, 30 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -1027,11 +1027,13 @@ struct mtk_soc_data {
+  * @regmap:            The register map pointing at the range used to setup
+  *                     SGMII modes
+  * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
++ * @interface:         Currently configured interface mode
+  * @pcs:               Phylink PCS structure
+  */
+ struct mtk_pcs {
+ 	struct regmap	*regmap;
+ 	u32             ana_rgc3;
++	phy_interface_t	interface;
+ 	struct phylink_pcs pcs;
+ };
+ 
+--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
+@@ -24,6 +24,10 @@ static int mtk_pcs_setup_mode_an(struct
+ {
+ 	unsigned int val;
+ 
++	regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
++	val &= ~RG_PHY_SPEED_MASK;
++	regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
++
+ 	/* Setup the link timer and QPHY power up inside SGMIISYS */
+ 	regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
+ 		     SGMII_LINK_TIMER_DEFAULT);
+@@ -36,9 +40,6 @@ static int mtk_pcs_setup_mode_an(struct
+ 	val |= SGMII_AN_RESTART;
+ 	regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
+ 
+-	regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
+-	val &= ~SGMII_PHYA_PWD;
+-	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
+ 
+ 	return 0;
+ 
+@@ -69,11 +70,6 @@ static int mtk_pcs_setup_mode_force(stru
+ 	val |= SGMII_SPEED_1000;
+ 	regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
+ 
+-	/* Release PHYA power down state */
+-	regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
+-	val &= ~SGMII_PHYA_PWD;
+-	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
+-
+ 	return 0;
+ }
+ 
+@@ -85,12 +81,32 @@ static int mtk_pcs_config(struct phylink
+ 	struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
+ 	int err = 0;
+ 
++	if (mpcs->interface != interface) {
++		/* PHYA power down */
++		regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
++				   SGMII_PHYA_PWD, SGMII_PHYA_PWD);
++
++		mpcs->interface = interface;
++	}
++
+ 	/* Setup SGMIISYS with the determined property */
+ 	if (interface != PHY_INTERFACE_MODE_SGMII)
+ 		err = mtk_pcs_setup_mode_force(mpcs, interface);
+ 	else if (phylink_autoneg_inband(mode))
+ 		err = mtk_pcs_setup_mode_an(mpcs);
+ 
++	/* Release PHYA power down state
++	 * Only removing bit SGMII_PHYA_PWD isn't enough.
++	 * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
++	 * prevents SGMII from working. The SGMII still shows link but no traffic
++	 * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
++	 * taken from a good working state of the SGMII interface.
++	 * Unknown how much the QPHY needs but it is racy without a sleep.
++	 * Tested on mt7622 & mt7986.
++	 */
++	usleep_range(50, 100);
++	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
++
+ 	return err;
+ }
+ 
+@@ -145,6 +161,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
+ 			return PTR_ERR(ss->pcs[i].regmap);
+ 
+ 		ss->pcs[i].pcs.ops = &mtk_pcs_ops;
++		ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
+ 	}
+ 
+ 	return 0;

target/linux/generic/backport-5.15/733-v6.2-03-net-mediatek-sgmii-fix-duplex-configuration.patch

@@ -0,0 +1,60 @@
+From 9d32637122de88f1ef614c29703f0e050cad342e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= <[email protected]>
+Date: Wed, 1 Feb 2023 19:23:30 +0100
+Subject: [PATCH] net: mediatek: sgmii: fix duplex configuration
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The logic of the duplex bit is inverted.  Setting it means half
+duplex, not full duplex.
+
+Fix and rename macro to avoid confusion.
+
+Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
+Reviewed-by: Russell King (Oracle) <[email protected]>
+Signed-off-by: Bjørn Mork <[email protected]>
+Acked-by: Daniel Golle <[email protected]>
+Tested-by: Daniel Golle <[email protected]>
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
+ drivers/net/ethernet/mediatek/mtk_sgmii.c   | 6 +++---
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -496,7 +496,7 @@
+ #define SGMII_SPEED_10			FIELD_PREP(SGMII_SPEED_MASK, 0)
+ #define SGMII_SPEED_100			FIELD_PREP(SGMII_SPEED_MASK, 1)
+ #define SGMII_SPEED_1000		FIELD_PREP(SGMII_SPEED_MASK, 2)
+-#define SGMII_DUPLEX_FULL		BIT(4)
++#define SGMII_DUPLEX_HALF		BIT(4)
+ #define SGMII_IF_MODE_BIT5		BIT(5)
+ #define SGMII_REMOTE_FAULT_DIS		BIT(8)
+ #define SGMII_CODE_SYNC_SET_VAL		BIT(9)
+--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
+@@ -66,7 +66,7 @@ static int mtk_pcs_setup_mode_force(stru
+ 
+ 	/* Set the speed etc but leave the duplex unchanged */
+ 	regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
+-	val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
++	val &= SGMII_DUPLEX_HALF | ~SGMII_IF_MODE_MASK;
+ 	val |= SGMII_SPEED_1000;
+ 	regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
+ 
+@@ -131,9 +131,10 @@ static void mtk_pcs_link_up(struct phyli
+ 
+ 	/* SGMII force duplex setting */
+ 	regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
+-	val &= ~SGMII_DUPLEX_FULL;
+-	if (duplex == DUPLEX_FULL)
+-		val |= SGMII_DUPLEX_FULL;
++
++	val &= ~SGMII_DUPLEX_HALF;
++	if (duplex != DUPLEX_FULL)
++		val |= SGMII_DUPLEX_HALF;
+ 
+ 	regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
+ }

target/linux/generic/backport-5.15/733-v6.2-04-mtk_sgmii-enable-PCS-polling-to-allow-SFP-work.patch

@@ -0,0 +1,33 @@
+From 3337a6e04ddf2923a1bdcf3d31b3b52412bf82dd Mon Sep 17 00:00:00 2001
+From: Alexander Couzens <[email protected]>
+Date: Wed, 1 Feb 2023 19:23:31 +0100
+Subject: [PATCH] mtk_sgmii: enable PCS polling to allow SFP work
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently there is no IRQ handling (even the SGMII supports it).
+Enable polling to support SFP ports.
+
+Fixes: 14a44ab0330d ("net: mtk_eth_soc: partially convert to phylink_pcs")
+Reviewed-by: Russell King (Oracle) <[email protected]>
+Signed-off-by: Alexander Couzens <[email protected]>
+[ bmork: changed "1" => "true" ]
+Signed-off-by: Bjørn Mork <[email protected]>
+Acked-by: Daniel Golle <[email protected]>
+Tested-by: Daniel Golle <[email protected]>
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_sgmii.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
+@@ -162,6 +162,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
+ 			return PTR_ERR(ss->pcs[i].regmap);
+ 
+ 		ss->pcs[i].pcs.ops = &mtk_pcs_ops;
++		ss->pcs[i].pcs.poll = true;
+ 		ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
+ 	}
+ 

target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch

@@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle <[email protected]>
 
 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
-@@ -122,10 +122,28 @@ static void mtk_pcs_link_up(struct phyli
+@@ -143,10 +143,28 @@ static void mtk_pcs_link_up(struct phyli
  	regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  }
  

target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch

@@ -1,39 +0,0 @@
-From 7f75f43fe2159123baa101fcc8c6faa0b0a4c598 Mon Sep 17 00:00:00 2001
-From: Alexander Couzens <[email protected]>
-Date: Sat, 13 Aug 2022 14:48:51 +0200
-Subject: [PATCH 05/10] net: mtk_sgmii: fix powering up the SGMII phy
-
-There are certain race condition when the SGMII_PHYA_PWD register still
-contains 0x9 which prevents the SGMII from working properly.
-
-The SGMII still shows link but no traffic can flow.
-
-Signed-off-by: Alexander Couzens <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
-+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
-@@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct
- 	val |= SGMII_AN_RESTART;
- 	regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
- 
--	regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
--	val &= ~SGMII_PHYA_PWD;
--	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
-+	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
- 
- 	return 0;
- 
-@@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(stru
- 	regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
- 
- 	/* Release PHYA power down state */
--	regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
--	val &= ~SGMII_PHYA_PWD;
--	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
-+	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
- 
- 	return 0;
- }

target/linux/generic/pending-5.15/726-net-mtk_sgmii-ensure-the-SGMII-PHY-is-powered-down-o.patch

@@ -1,65 +0,0 @@
-From 9daea9b71d060d93d7394ac465b2e5ee0b7e7bca Mon Sep 17 00:00:00 2001
-From: Alexander Couzens <[email protected]>
-Date: Mon, 15 Aug 2022 16:02:01 +0200
-Subject: [PATCH 06/10] net: mtk_sgmii: ensure the SGMII PHY is powered down on
- configuration
-
-The code expect the PHY to be in power down (which is only true after reset).
-Allow the changes of SGMII parameters more than once.
----
- drivers/net/ethernet/mediatek/mtk_sgmii.c | 16 +++++++++++++++-
- 1 file changed, 15 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
-+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
-@@ -7,6 +7,7 @@
-  *
-  */
- 
-+#include <linux/delay.h>
- #include <linux/mfd/syscon.h>
- #include <linux/of.h>
- #include <linux/phylink.h>
-@@ -24,6 +25,9 @@ static int mtk_pcs_setup_mode_an(struct
- {
- 	unsigned int val;
- 
-+	/* PHYA power down */
-+	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
-+
- 	/* Setup the link timer and QPHY power up inside SGMIISYS */
- 	regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
- 		     SGMII_LINK_TIMER_DEFAULT);
-@@ -36,6 +40,10 @@ static int mtk_pcs_setup_mode_an(struct
- 	val |= SGMII_AN_RESTART;
- 	regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
- 
-+	/* Release PHYA power down state
-+	 * unknown how much the QPHY needs but it is racy without a sleep
-+	 */
-+	usleep_range(50, 100);
- 	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
- 
- 	return 0;
-@@ -50,6 +58,9 @@ static int mtk_pcs_setup_mode_force(stru
- {
- 	unsigned int val;
- 
-+	/* PHYA power down */
-+	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
-+
- 	regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
- 	val &= ~RG_PHY_SPEED_MASK;
- 	if (interface == PHY_INTERFACE_MODE_2500BASEX)
-@@ -67,7 +78,10 @@ static int mtk_pcs_setup_mode_force(stru
- 	val |= SGMII_SPEED_1000;
- 	regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
- 
--	/* Release PHYA power down state */
-+	/* Release PHYA power down state
-+	 * unknown how much the QPHY needs but it is racy without a sleep
-+	 */
-+	usleep_range(50, 100);
- 	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
- 
- 	return 0;

target/linux/generic/pending-5.15/727-net-mtk_sgmii-mtk_pcs_setup_mode_an-don-t-rely-on-re.patch

@@ -28,4 +28,4 @@ Signed-off-by: Alexander Couzens <[email protected]>
 +	val |= SGMII_AN_RESTART | SGMII_AN_ENABLE;
  	regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
  
- 	/* Release PHYA power down state
+ 

target/linux/generic/pending-5.15/728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch

@@ -14,7 +14,7 @@ Signed-off-by: Alexander Couzens <[email protected]>
 
 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
-@@ -21,13 +21,20 @@ static struct mtk_pcs *pcs_to_mtk_pcs(st
+@@ -20,12 +20,14 @@ static struct mtk_pcs *pcs_to_mtk_pcs(st
  }
  
  /* For SGMII interface mode */
@@ -23,25 +23,19 @@ Signed-off-by: Alexander Couzens <[email protected]>
  {
  	unsigned int val;
  
- 	/* PHYA power down */
- 	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
- 
-+	/* Set SGMII phy speed */
-+	regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
-+	val &= ~RG_PHY_SPEED_MASK;
+ 	regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
+ 	val &= ~RG_PHY_SPEED_MASK;
 +	if (interface == PHY_INTERFACE_MODE_2500BASEX)
 +		val |= RG_PHY_SPEED_3_125G;
-+	regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
-+
+ 	regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
+ 
  	/* Setup the link timer and QPHY power up inside SGMIISYS */
- 	regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
- 		     SGMII_LINK_TIMER_DEFAULT);
-@@ -100,7 +107,7 @@ static int mtk_pcs_config(struct phylink
+@@ -98,7 +100,7 @@ static int mtk_pcs_config(struct phylink
  	if (interface != PHY_INTERFACE_MODE_SGMII)
  		err = mtk_pcs_setup_mode_force(mpcs, interface);
  	else if (phylink_autoneg_inband(mode))
 -		err = mtk_pcs_setup_mode_an(mpcs);
 +		err = mtk_pcs_setup_mode_an(mpcs, interface);
  
- 	return err;
- }
+ 	/* Release PHYA power down state
+ 	 * Only removing bit SGMII_PHYA_PWD isn't enough.

target/linux/generic/pending-5.15/729-net-mtk_eth_soc-improve-comment.patch

@@ -10,7 +10,7 @@ Signed-off-by: Alexander Couzens <[email protected]>
 
 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
-@@ -80,7 +80,8 @@ static int mtk_pcs_setup_mode_force(stru
+@@ -67,7 +67,8 @@ static int mtk_pcs_setup_mode_force(stru
  	val &= ~SGMII_AN_ENABLE;
  	regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
  
@@ -18,5 +18,5 @@ Signed-off-by: Alexander Couzens <[email protected]>
 +	/* Set the speed etc but leave the duplex unchanged.
 +	 * The SGMII mode for 2.5gbit is the same as for 1gbit, expect the speed in ANA_RGC3 */
  	regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
- 	val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
+ 	val &= SGMII_DUPLEX_HALF | ~SGMII_IF_MODE_MASK;
  	val |= SGMII_SPEED_1000;

target/linux/generic/pending-5.15/730-mtk_sgmii-enable-PCS-polling-to-allow-SFP-work.patch

@@ -1,23 +0,0 @@
-From 95dcd0f223d7cab6e25bc19088016e5eb4ca1804 Mon Sep 17 00:00:00 2001
-From: Alexander Couzens <[email protected]>
-Date: Tue, 16 Aug 2022 00:22:11 +0200
-Subject: [PATCH 10/10] mtk_sgmii: enable PCS polling to allow SFP work
-
-Currently there is no IRQ handling (even the SGMII supports it).
-Enable polling to support SFP ports.
-
-Signed-off-by: Alexander Couzens <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_sgmii.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
-+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
-@@ -182,6 +182,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
- 			return PTR_ERR(ss->pcs[i].regmap);
- 
- 		ss->pcs[i].pcs.ops = &mtk_pcs_ops;
-+		ss->pcs[i].pcs.poll = 1;
- 	}
- 
- 	return 0;

target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch

@@ -90,7 +90,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1007,6 +1007,7 @@ struct mtk_soc_data {
+@@ -1012,6 +1012,7 @@ struct mtk_soc_data {
  	u8		hash_offset;
  	u16		foe_entry_size;
  	netdev_features_t hw_features;
@@ -171,7 +171,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	dma_wmb();
  
  	mtk_ppe_cache_clear(ppe);
-@@ -743,14 +793,42 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
+@@ -742,14 +792,42 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
  	return mtk_ppe_wait_busy(ppe);
  }
  
@@ -215,7 +215,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  
  	ppe = devm_kzalloc(dev, sizeof(*ppe), GFP_KERNEL);
  	if (!ppe)
-@@ -765,6 +843,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+@@ -764,6 +842,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
  	ppe->eth = eth;
  	ppe->dev = dev;
  	ppe->version = version;
@@ -223,7 +223,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  
  	foe = dmam_alloc_coherent(ppe->dev,
  				  MTK_PPE_ENTRIES * soc->foe_entry_size,
-@@ -780,6 +859,25 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+@@ -779,6 +858,25 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
  	if (!ppe->foe_flow)
  		return NULL;
  
@@ -249,7 +249,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	mtk_ppe_debugfs_init(ppe, index);
  
  	return ppe;
-@@ -894,6 +992,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+@@ -893,6 +991,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
  		ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
  		ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
  	}
@@ -276,7 +276,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  #define MTK_FOE_IB2_WDMA_DEVIDX		BIT(16)
  #define MTK_FOE_IB2_WDMA_WINFO		BIT(17)
  
-@@ -284,16 +285,34 @@ struct mtk_flow_entry {
+@@ -283,16 +284,34 @@ struct mtk_flow_entry {
  	unsigned long cookie;
  };
  
@@ -311,7 +311,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	u16 foe_check_time[MTK_PPE_ENTRIES];
  	struct hlist_head *foe_flow;
  
-@@ -303,7 +322,7 @@ struct mtk_ppe {
+@@ -302,7 +321,7 @@ struct mtk_ppe {
  };
  
  struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
@@ -320,7 +320,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  void mtk_ppe_start(struct mtk_ppe *ppe);
  int mtk_ppe_stop(struct mtk_ppe *ppe);
  int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);
-@@ -355,5 +374,7 @@ int mtk_foe_entry_commit(struct mtk_ppe
+@@ -354,5 +373,7 @@ int mtk_foe_entry_commit(struct mtk_ppe
  void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
  int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
  int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index);

target/linux/generic/pending-5.15/732-04-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch

@@ -628,7 +628,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  
  /* PDMA on MT7628 */
  #define TX_DMA_DONE		BIT(31)
-@@ -952,6 +971,7 @@ struct mtk_reg_map {
+@@ -957,6 +976,7 @@ struct mtk_reg_map {
  	} pdma;
  	struct {
  		u32	qtx_cfg;	/* tx queue configuration */
@@ -636,7 +636,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  		u32	rx_ptr;		/* rx base pointer */
  		u32	rx_cnt_cfg;	/* rx max count configuration */
  		u32	qcrx_ptr;	/* rx cpu pointer */
-@@ -969,6 +989,7 @@ struct mtk_reg_map {
+@@ -974,6 +994,7 @@ struct mtk_reg_map {
  		u32	fq_tail;	/* fq tail pointer */
  		u32	fq_count;	/* fq free page count */
  		u32	fq_blen;	/* fq free page buffer length */
@@ -644,7 +644,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  	} qdma;
  	u32	gdm1_cnt;
  	u32	gdma_to_ppe0;
-@@ -1173,6 +1194,7 @@ struct mtk_mac {
+@@ -1180,6 +1201,7 @@ struct mtk_mac {
  	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
  	int				hwlro_ip_cnt;
  	unsigned int			syscfg0;

target/linux/generic/pending-5.15/732-06-net-ethernet-mediatek-ppe-assign-per-port-queues-for.patch

@@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  #define MTK_FOE_IB2_DEST_PORT_V2	GENMASK(12, 9)
  #define MTK_FOE_IB2_MULTICAST_V2	BIT(13)
  #define MTK_FOE_IB2_WDMA_WINFO_V2	BIT(19)
-@@ -370,6 +372,8 @@ int mtk_foe_entry_set_pppoe(struct mtk_e
+@@ -369,6 +371,8 @@ int mtk_foe_entry_set_pppoe(struct mtk_e
  			    int sid);
  int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry,
  			   int wdma_idx, int txq, int bss, int wcid);

target/linux/generic/pending-5.15/732-07-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch

@@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -916,7 +916,13 @@ enum mkt_eth_capabilities {
+@@ -921,7 +921,13 @@ enum mkt_eth_capabilities {
  #define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
  	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
  

target/linux/generic/pending-5.15/732-09-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch

@@ -181,7 +181,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  /* CDMP Ingress Control Register */
  #define MTK_CDMP_IG_CTRL	0x400
  #define MTK_CDMP_STAG_EN	BIT(0)
-@@ -1166,6 +1172,8 @@ struct mtk_eth {
+@@ -1173,6 +1179,8 @@ struct mtk_eth {
  
  	int				ip_align;
  

target/linux/generic/pending-5.15/733-01-net-ethernet-mtk_eth_soc-reset-PCS-state.patch

@@ -0,0 +1,44 @@
+From b66105968b8c37c26a75b9da9281cbc1c8f73594 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 22 Jan 2023 23:58:36 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: reset PCS state
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reset PCS state when changing interface mode.
+
+Reviewed-by: Russell King (Oracle) <[email protected]>
+Tested-by: Bjørn Mork <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
+ drivers/net/ethernet/mediatek/mtk_sgmii.c   | 4 ++++
+ 2 files changed, 8 insertions(+)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -504,6 +504,10 @@
+ #define SGMII_SEND_AN_ERROR_EN		BIT(11)
+ #define SGMII_IF_MODE_MASK		GENMASK(5, 1)
+ 
++/* Register to reset SGMII design */
++#define SGMII_RESERVED_0	0x34
++#define SGMII_SW_RESET		BIT(0)
++
+ /* Register to set SGMII speed, ANA RG_ Control Signals III*/
+ #define SGMSYS_ANA_RG_CS3	0x2028
+ #define RG_PHY_SPEED_MASK	(BIT(2) | BIT(3))
+--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
+@@ -86,6 +86,10 @@ static int mtk_pcs_config(struct phylink
+ 		regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
+ 				   SGMII_PHYA_PWD, SGMII_PHYA_PWD);
+ 
++		/* Reset SGMII PCS state */
++		regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
++				   SGMII_SW_RESET, SGMII_SW_RESET);
++
+ 		mpcs->interface = interface;
+ 	}
+ 

target/linux/generic/pending-5.15/733-02-net-ethernet-mtk_eth_soc-fix-RX-data-corruption-issu.patch

@@ -0,0 +1,46 @@
+From e0eb504b1c9f973427a33d7ffef29ddecdb464b9 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Mon, 23 Jan 2023 00:56:02 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: fix RX data corruption issue
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Also set bit 12 when setting up MAC MCR, as MediaTek SDK did the same
+change stating:
+"If without this patch, kernel might receive invalid packets that are
+corrupted by GMAC."[1]
+This fixes issues with <= 1G speed where we could previously observe
+about 30% packet loss while the bad packet counter was increasing.
+Unfortunately the meaning of bit 12 is not documented anywhere in SDK
+code or datasheets.
+
+[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/d8a2975939a12686c4a95c40db21efdc3f821f63
+Tested-by: Bjørn Mork <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -523,7 +523,7 @@ static int mtk_mac_finish(struct phylink
+ 	/* Setup gmac */
+ 	mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
+ 	mcr_new = mcr_cur;
+-	mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
++	mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_BIT_12 | MAC_MCR_FORCE_MODE |
+ 		   MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
+ 
+ 	/* Only update control register when needed! */
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -367,6 +367,7 @@
+ #define MAC_MCR_FORCE_MODE	BIT(15)
+ #define MAC_MCR_TX_EN		BIT(14)
+ #define MAC_MCR_RX_EN		BIT(13)
++#define MAC_MCR_BIT_12		BIT(12)
+ #define MAC_MCR_BACKOFF_EN	BIT(9)
+ #define MAC_MCR_BACKPR_EN	BIT(8)
+ #define MAC_MCR_FORCE_RX_FC	BIT(5)

target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch

@@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  #include <net/dsa.h>
  #include "mtk_eth_soc.h"
  #include "mtk_ppe.h"
-@@ -756,7 +757,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe
+@@ -755,7 +756,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe
  		    skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
  			goto out;