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@@ -1,341 +0,0 @@
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---- a/drivers/spi/Kconfig
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-+++ b/drivers/spi/Kconfig
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-@@ -330,6 +330,12 @@ config SPI_DLN2
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- This driver can also be built as a module. If so, the module
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- will be called spi-dln2.
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-
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-+config SPI_AIROHA_EN7523
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-+ bool "Airoha EN7523 SPI controller support"
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-+ depends on ARCH_AIROHA
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-+ help
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-+ This enables SPI controller support for the Airoha EN7523 SoC.
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-+
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- config SPI_EP93XX
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- tristate "Cirrus Logic EP93xx SPI controller"
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- depends on ARCH_EP93XX || COMPILE_TEST
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---- a/drivers/spi/Makefile
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-+++ b/drivers/spi/Makefile
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-@@ -47,6 +47,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.
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- obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
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- obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
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- obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
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-+obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o
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- obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
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- obj-$(CONFIG_SPI_FSI) += spi-fsi.o
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- obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
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---- /dev/null
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-+++ b/drivers/spi/spi-en7523.c
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-@@ -0,0 +1,313 @@
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-+// SPDX-License-Identifier: GPL-2.0
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-+
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-+#include <linux/module.h>
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-+#include <linux/platform_device.h>
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-+#include <linux/mod_devicetable.h>
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-+#include <linux/spi/spi.h>
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-+
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-+
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-+#define ENSPI_READ_IDLE_EN 0x0004
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-+#define ENSPI_MTX_MODE_TOG 0x0014
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-+#define ENSPI_RDCTL_FSM 0x0018
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-+#define ENSPI_MANUAL_EN 0x0020
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-+#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024
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-+#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028
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-+#define ENSPI_MANUAL_OPFIFO_FULL 0x002C
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-+#define ENSPI_MANUAL_OPFIFO_WR 0x0030
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-+#define ENSPI_MANUAL_DFIFO_FULL 0x0034
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-+#define ENSPI_MANUAL_DFIFO_WDATA 0x0038
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-+#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C
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-+#define ENSPI_MANUAL_DFIFO_RD 0x0040
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-+#define ENSPI_MANUAL_DFIFO_RDATA 0x0044
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-+#define ENSPI_IER 0x0090
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-+#define ENSPI_NFI2SPI_EN 0x0130
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-+
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-+// TODO not in spi block
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-+#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4)
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-+
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-+#define OP_CSH 0x00
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-+#define OP_CSL 0x01
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-+#define OP_CK 0x02
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-+#define OP_OUTS 0x08
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-+#define OP_OUTD 0x09
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-+#define OP_OUTQ 0x0A
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-+#define OP_INS 0x0C
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-+#define OP_INS0 0x0D
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-+#define OP_IND 0x0E
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-+#define OP_INQ 0x0F
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-+#define OP_OS2IS 0x10
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-+#define OP_OS2ID 0x11
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-+#define OP_OS2IQ 0x12
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-+#define OP_OD2IS 0x13
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-+#define OP_OD2ID 0x14
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-+#define OP_OD2IQ 0x15
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-+#define OP_OQ2IS 0x16
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-+#define OP_OQ2ID 0x17
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-+#define OP_OQ2IQ 0x18
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-+#define OP_OSNIS 0x19
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-+#define OP_ODNID 0x1A
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-+
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-+#define MATRIX_MODE_AUTO 1
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-+#define CONF_MTX_MODE_AUTO 0
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-+#define MANUALEN_AUTO 0
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-+#define MATRIX_MODE_MANUAL 0
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-+#define CONF_MTX_MODE_MANUAL 9
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-+#define MANUALEN_MANUAL 1
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-+
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-+#define _ENSPI_MAX_XFER 0x1ff
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-+
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-+#define REG(x) (iobase + x)
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-+
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-+
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-+static void __iomem *iobase;
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-+
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-+
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-+static void opfifo_write(u32 cmd, u32 len)
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-+{
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-+ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
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-+
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-+ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
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-+
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-+ /* Wait for room in OPFIFO */
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-+ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
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-+ ;
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-+
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-+ /* Shift command into OPFIFO */
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-+ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
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-+
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-+ /* Wait for command to finish */
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-+ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
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-+ ;
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-+}
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-+
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-+static void set_cs(int state)
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-+{
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-+ if (state)
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-+ opfifo_write(OP_CSH, 1);
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-+ else
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-+ opfifo_write(OP_CSL, 1);
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-+}
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-+
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-+static void manual_begin_cmd(void)
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-+{
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-+ /* Disable read idle state */
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-+ writel(0, REG(ENSPI_READ_IDLE_EN));
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-+
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-+ /* Wait for FSM to reach idle state */
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-+ while (readl(REG(ENSPI_RDCTL_FSM)))
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-+ ;
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-+
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-+ /* Set SPI core to manual mode */
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-+ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
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-+ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
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-+}
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-+
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-+static void manual_end_cmd(void)
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-+{
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-+ /* Set SPI core to auto mode */
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-+ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
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-+ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
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-+
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-+ /* Enable read idle state */
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-+ writel(1, REG(ENSPI_READ_IDLE_EN));
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-+}
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-+
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-+static void dfifo_read(u8 *buf, int len)
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-+{
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-+ int i;
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-+
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-+ for (i = 0; i < len; i++) {
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-+ /* Wait for requested data to show up in DFIFO */
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-+ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
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-+ ;
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-+ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
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-+ /* Queue up next byte */
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-+ writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
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-+ }
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-+}
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-+
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-+static void dfifo_write(const u8 *buf, int len)
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-+{
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-+ int i;
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-+
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-+ for (i = 0; i < len; i++) {
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-+ /* Wait for room in DFIFO */
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-+ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
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-+ ;
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-+ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
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-+ }
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-+}
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-+
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-+#if 0
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-+static void set_spi_clock_speed(int freq_mhz)
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-+{
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-+ u32 tmp, val;
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-+
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-+ tmp = readl(ENSPI_CLOCK_DIVIDER);
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-+ tmp &= 0xffff0000;
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-+ writel(tmp, ENSPI_CLOCK_DIVIDER);
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-+
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-+ val = (400 / (freq_mhz * 2));
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-+ tmp |= (val << 8) | 1;
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-+ writel(tmp, ENSPI_CLOCK_DIVIDER);
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-+}
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-+#endif
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-+
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-+static void init_hw(void)
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-+{
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-+ /* Disable manual/auto mode clash interrupt */
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-+ writel(0, REG(ENSPI_IER));
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-+
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-+ // TODO via clk framework
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-+ // set_spi_clock_speed(50);
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-+
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-+ /* Disable DMA */
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-+ writel(0, REG(ENSPI_NFI2SPI_EN));
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-+}
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-+
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-+static int xfer_read(struct spi_transfer *xfer)
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-+{
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-+ int opcode;
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-+ uint8_t *buf = xfer->rx_buf;
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-+
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-+ switch (xfer->rx_nbits) {
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-+ case SPI_NBITS_SINGLE:
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-+ opcode = OP_INS;
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-+ break;
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-+ case SPI_NBITS_DUAL:
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-+ opcode = OP_IND;
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-+ break;
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-+ case SPI_NBITS_QUAD:
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-+ opcode = OP_INQ;
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-+ break;
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-+ }
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-+
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-+ opfifo_write(opcode, xfer->len);
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-+ dfifo_read(buf, xfer->len);
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-+
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-+ return xfer->len;
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-+}
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-+
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-+static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
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-+{
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-+ int opcode;
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-+ const uint8_t *buf = xfer->tx_buf;
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-+
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-+ if (next_xfer_is_rx) {
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-+ /* need to use Ox2Ix opcode to set the core to input afterwards */
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-+ switch (xfer->tx_nbits) {
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-+ case SPI_NBITS_SINGLE:
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-+ opcode = OP_OS2IS;
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-+ break;
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-+ case SPI_NBITS_DUAL:
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-+ opcode = OP_OS2ID;
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-+ break;
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-+ case SPI_NBITS_QUAD:
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-+ opcode = OP_OS2IQ;
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-+ break;
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-+ }
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-+ } else {
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-+ switch (xfer->tx_nbits) {
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-+ case SPI_NBITS_SINGLE:
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-+ opcode = OP_OUTS;
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-+ break;
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-+ case SPI_NBITS_DUAL:
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-+ opcode = OP_OUTD;
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-+ break;
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-+ case SPI_NBITS_QUAD:
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-+ opcode = OP_OUTQ;
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-+ break;
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-+ }
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-+ }
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-+
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-+ opfifo_write(opcode, xfer->len);
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-+ dfifo_write(buf, xfer->len);
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-+
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-+ return xfer->len;
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-+}
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-+
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-+size_t max_transfer_size(struct spi_device *spi)
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-+{
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-+ return _ENSPI_MAX_XFER;
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-+}
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-+
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-+int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
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-+{
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-+ struct spi_transfer *xfer;
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-+ int next_xfer_is_rx = 0;
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-+
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-+ manual_begin_cmd();
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-+ set_cs(0);
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-+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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-+ if (xfer->tx_buf) {
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-+ if (!list_is_last(&xfer->transfer_list, &msg->transfers)
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-+ && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
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-+ next_xfer_is_rx = 1;
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-+ else
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-+ next_xfer_is_rx = 0;
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-+ msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
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-+ } else if (xfer->rx_buf) {
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-+ msg->actual_length += xfer_read(xfer);
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-+ }
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-+ }
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-+ set_cs(1);
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-+ manual_end_cmd();
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-+
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-+ msg->status = 0;
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-+ spi_finalize_current_message(ctrl);
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-+
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-+ return 0;
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-+}
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-+
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-+static int spi_probe(struct platform_device *pdev)
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-+{
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-+ struct spi_controller *ctrl;
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-+ int err;
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-+
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-+ ctrl = devm_spi_alloc_master(&pdev->dev, 0);
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-+ if (!ctrl) {
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-+ dev_err(&pdev->dev, "Error allocating SPI controller\n");
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-+ return -ENOMEM;
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-+ }
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-+
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-+ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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-+ if (IS_ERR(iobase)) {
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-+ dev_err(&pdev->dev, "Could not map SPI register address");
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-+ return -ENOMEM;
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-+ }
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-+
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-+ init_hw();
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-+
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-+ ctrl->dev.of_node = pdev->dev.of_node;
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-+ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
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-+ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
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-+ ctrl->max_transfer_size = max_transfer_size;
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-+ ctrl->transfer_one_message = transfer_one_message;
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-+ err = devm_spi_register_controller(&pdev->dev, ctrl);
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-+ if (err) {
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-+ dev_err(&pdev->dev, "Could not register SPI controller\n");
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-+ return -ENODEV;
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-+ }
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-+
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-+ return 0;
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-+}
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-+
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-+static const struct of_device_id spi_of_ids[] = {
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-+ { .compatible = "airoha,en7523-spi" },
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-+ { /* sentinel */ }
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-+};
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-+MODULE_DEVICE_TABLE(of, spi_of_ids);
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-+
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-+static struct platform_driver spi_driver = {
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-+ .probe = spi_probe,
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-+ .driver = {
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-+ .name = "airoha-en7523-spi",
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-+ .of_match_table = spi_of_ids,
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-+ },
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-+};
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-+
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-+module_platform_driver(spi_driver);
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-+
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-+MODULE_LICENSE("GPL v2");
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-+MODULE_AUTHOR("Bert Vermeulen <[email protected]>");
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-+MODULE_DESCRIPTION("Airoha EN7523 SPI driver");
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Robert Marko