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+From b01d622d76134e9401970ffd3fbbb9a7051f976a Mon Sep 17 00:00:00 2001
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+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
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+Date: Tue, 20 Sep 2022 14:11:54 +0200
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+Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Reset COMPHY registers
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+ before USB 3.0 power on
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+MIME-Version: 1.0
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+Content-Type: text/plain; charset=UTF-8
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+Content-Transfer-Encoding: 8bit
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+
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+Turris MOX board with older ARM Trusted Firmware version v1.5 is not able
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+to detect any USB 3.0 device connected to USB-A port on Mox-A module after
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+commit 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken
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+reset support"). On the other hand USB 2.0 devices connected to the same
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+USB-A port are working fine.
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+
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+It looks as if the older firmware configures COMPHY registers for USB 3.0
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+somehow incompatibly for kernel driver. Experiments show that resetting
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+COMPHY registers via setting SFT_RST auto-clearing bit in COMPHY_SFT_RESET
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+register fixes this issue.
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+
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+Reset the COMPHY in mvebu_a3700_comphy_usb3_power_on() function as a first
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+step after selecting COMPHY lane and USB 3.0 function. With this change
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+Turris MOX board can successfully detect USB 3.0 devices again.
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+
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+Before the above mentioned commit this reset was implemented in PHY reset
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+method, so this is the reason why there was no issue with older firmware
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+version then.
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+
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+Fixes: 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset support")
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+Reported-by: Marek Behún <[email protected]>
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+Signed-off-by: Pali Rohár <[email protected]>
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+Tested-by: Shin'ichiro Kawasaki <[email protected]>
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+Link: https://lore.kernel.org/r/[email protected]
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+Signed-off-by: Vinod Koul <[email protected]>
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+---
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+ drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 +++
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+ 1 file changed, 3 insertions(+)
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+
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+--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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+@@ -826,6 +826,9 @@ mvebu_a3700_comphy_usb3_power_on(struct
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+ if (ret)
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+ return ret;
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+
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++ /* COMPHY register reset (cleared automatically) */
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++ comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
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++
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+ /*
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+ * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
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+ * register belong to UTMI module, so it is set in UTMI phy driver.
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