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+From d291fbb8245d5ba04979fed85575860a5cea7196 Mon Sep 17 00:00:00 2001
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+From: Matthew Hagan <[email protected]>
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+Date: Thu, 14 Oct 2021 00:39:21 +0200
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+Subject: dt-bindings: net: dsa: qca8k: convert to YAML schema
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+
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+Convert the qca8k bindings to YAML format.
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+
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+Signed-off-by: Matthew Hagan <[email protected]>
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+Co-developed-by: Ansuel Smith <[email protected]>
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+Signed-off-by: Ansuel Smith <[email protected]>
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+Signed-off-by: David S. Miller <[email protected]>
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+---
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+ .../devicetree/bindings/net/dsa/qca8k.txt | 245 --------------
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+ .../devicetree/bindings/net/dsa/qca8k.yaml | 362 +++++++++++++++++++++
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+ 2 files changed, 362 insertions(+), 245 deletions(-)
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+ delete mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.txt
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+ create mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.yaml
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+
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+--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
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++++ /dev/null
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+@@ -1,245 +0,0 @@
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+-* Qualcomm Atheros QCA8xxx switch family
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+-
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+-Required properties:
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+-
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+-- compatible: should be one of:
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+- "qca,qca8328": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
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+- "qca,qca8327": referenced as AR8327(N)-AL1A DR-QFN 148 pin package
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+- "qca,qca8334": referenced as QCA8334-AL3C QFN 88 pin package
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+- "qca,qca8337": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
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+-
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+-- #size-cells: must be 0
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+-- #address-cells: must be 1
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+-
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+-Optional properties:
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+-
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+-- reset-gpios: GPIO to be used to reset the whole device
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+-- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open
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+- drain or eeprom presence. This is needed for broken
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+- devices that have wrong configuration or when the oem
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+- decided to not use pin strapping and fallback to sw
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+- regs.
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+-- qca,led-open-drain: Set leds to open-drain mode. This requires the
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+- qca,ignore-power-on-sel to be set or the driver will fail
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+- to probe. This is needed if the oem doesn't use pin
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+- strapping to set this mode and prefers to set it using sw
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+- regs. The pin strapping related to led open drain mode is
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+- the pin B68 for QCA832x and B49 for QCA833x
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+-
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+-Subnodes:
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+-
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+-The integrated switch subnode should be specified according to the binding
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+-described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
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+-mdio-bus each subnode describing a port needs to have a valid phandle
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+-referencing the internal PHY it is connected to. This is because there's no
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+-N:N mapping of port and PHY id.
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+-To declare the internal mdio-bus configuration, declare a mdio node in the
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+-switch node and declare the phandle for the port referencing the internal
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+-PHY is connected to. In this config a internal mdio-bus is registered and
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+-the mdio MASTER is used as communication.
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+-
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+-Don't use mixed external and internal mdio-bus configurations, as this is
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+-not supported by the hardware.
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+-
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+-This switch support 2 CPU port. Normally and advised configuration is with
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+-CPU port set to port 0. It is also possible to set the CPU port to port 6
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+-if the device requires it. The driver will configure the switch to the defined
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+-port. With both CPU port declared the first CPU port is selected as primary
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+-and the secondary CPU ignored.
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+-
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+-A CPU port node has the following optional node:
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+-
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+-- fixed-link : Fixed-link subnode describing a link to a non-MDIO
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+- managed entity. See
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+- Documentation/devicetree/bindings/net/fixed-link.txt
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+- for details.
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+-- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.
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+- Mostly used in qca8327 with CPU port 0 set to
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+- sgmii.
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+-- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
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+-- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX
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+- chain along with Signal Detection.
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+- This should NOT be enabled for qca8327. If enabled with
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+- qca8327 the sgmii port won't correctly init and an err
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+- is printed.
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+- This can be required for qca8337 switch with revision 2.
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+- A warning is displayed when used with revision greater
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+- 2.
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+- With CPU port set to sgmii and qca8337 it is advised
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+- to set this unless a communication problem is observed.
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+-
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+-For QCA8K the 'fixed-link' sub-node supports only the following properties:
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+-
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+-- 'speed' (integer, mandatory), to indicate the link speed. Accepted
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+- values are 10, 100 and 1000
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+-- 'full-duplex' (boolean, optional), to indicate that full duplex is
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+- used. When absent, half duplex is assumed.
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+-
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+-Examples:
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+-
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+-for the external mdio-bus configuration:
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+-
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+- &mdio0 {
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+- phy_port1: phy@0 {
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+- reg = <0>;
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+- };
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+-
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+- phy_port2: phy@1 {
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+- reg = <1>;
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+- };
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+-
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+- phy_port3: phy@2 {
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+- reg = <2>;
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+- };
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+-
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+- phy_port4: phy@3 {
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+- reg = <3>;
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+- };
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+-
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+- phy_port5: phy@4 {
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+- reg = <4>;
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+- };
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+-
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+- switch@10 {
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+- compatible = "qca,qca8337";
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+- #address-cells = <1>;
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+- #size-cells = <0>;
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+-
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+- reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
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+- reg = <0x10>;
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+-
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+- ports {
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+- #address-cells = <1>;
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+- #size-cells = <0>;
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+- port@0 {
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+- reg = <0>;
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+- label = "cpu";
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+- ethernet = <&gmac1>;
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+- phy-mode = "rgmii";
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+- fixed-link {
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+- speed = 1000;
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+- full-duplex;
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+- };
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+- };
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+-
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+- port@1 {
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+- reg = <1>;
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+- label = "lan1";
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+- phy-handle = <&phy_port1>;
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+- };
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+-
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+- port@2 {
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+- reg = <2>;
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+- label = "lan2";
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+- phy-handle = <&phy_port2>;
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+- };
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+-
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+- port@3 {
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+- reg = <3>;
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+- label = "lan3";
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+- phy-handle = <&phy_port3>;
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+- };
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+-
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+- port@4 {
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+- reg = <4>;
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+- label = "lan4";
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+- phy-handle = <&phy_port4>;
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+- };
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+-
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+- port@5 {
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+- reg = <5>;
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+- label = "wan";
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+- phy-handle = <&phy_port5>;
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+- };
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+- };
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+- };
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+- };
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+-
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+-for the internal master mdio-bus configuration:
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+-
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+- &mdio0 {
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+- switch@10 {
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+- compatible = "qca,qca8337";
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+- #address-cells = <1>;
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+- #size-cells = <0>;
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+-
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+- reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
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+- reg = <0x10>;
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+-
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+- ports {
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+- #address-cells = <1>;
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+- #size-cells = <0>;
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+-
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+- port@0 {
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+- reg = <0>;
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+- label = "cpu";
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+- ethernet = <&gmac1>;
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+- phy-mode = "rgmii";
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+- fixed-link {
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+- speed = 1000;
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+- full-duplex;
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+- };
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+- };
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+-
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+- port@1 {
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+- reg = <1>;
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+- label = "lan1";
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+- phy-mode = "internal";
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+- phy-handle = <&phy_port1>;
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+- };
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+-
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+- port@2 {
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+- reg = <2>;
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+- label = "lan2";
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+- phy-mode = "internal";
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+- phy-handle = <&phy_port2>;
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+- };
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+-
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+- port@3 {
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+- reg = <3>;
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+- label = "lan3";
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+- phy-mode = "internal";
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+- phy-handle = <&phy_port3>;
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+- };
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+-
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+- port@4 {
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+- reg = <4>;
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+- label = "lan4";
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+- phy-mode = "internal";
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+- phy-handle = <&phy_port4>;
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+- };
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+-
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+- port@5 {
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+- reg = <5>;
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+- label = "wan";
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+- phy-mode = "internal";
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+- phy-handle = <&phy_port5>;
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+- };
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+- };
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+-
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+- mdio {
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+- #address-cells = <1>;
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+- #size-cells = <0>;
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+-
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+- phy_port1: phy@0 {
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+- reg = <0>;
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+- };
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+-
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+- phy_port2: phy@1 {
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+- reg = <1>;
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+- };
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+-
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+- phy_port3: phy@2 {
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+- reg = <2>;
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+- };
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+-
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+- phy_port4: phy@3 {
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+- reg = <3>;
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+- };
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+-
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+- phy_port5: phy@4 {
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+- reg = <4>;
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+- };
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+- };
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+- };
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+- };
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+--- /dev/null
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++++ b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml
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+@@ -0,0 +1,362 @@
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++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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++%YAML 1.2
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++---
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++$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
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++$schema: http://devicetree.org/meta-schemas/core.yaml#
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++
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++title: Qualcomm Atheros QCA83xx switch family
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++
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++maintainers:
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++ - John Crispin <[email protected]>
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++
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++description:
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++ If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
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++ describing a port needs to have a valid phandle referencing the internal PHY
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++ it is connected to. This is because there is no N:N mapping of port and PHY
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++ ID. To declare the internal mdio-bus configuration, declare an MDIO node in
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++ the switch node and declare the phandle for the port, referencing the internal
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++ PHY it is connected to. In this config, an internal mdio-bus is registered and
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++ the MDIO master is used for communication. Mixed external and internal
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++ mdio-bus configurations are not supported by the hardware.
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++
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++properties:
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++ compatible:
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++ oneOf:
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++ - enum:
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++ - qca,qca8327
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++ - qca,qca8328
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++ - qca,qca8334
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++ - qca,qca8337
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++ description: |
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++ qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
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++ qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
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++ qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
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++ qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
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++
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++ reg:
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++ maxItems: 1
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++
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++ reset-gpios:
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++ description:
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++ GPIO to be used to reset the whole device
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++ maxItems: 1
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++
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++ qca,ignore-power-on-sel:
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++ $ref: /schemas/types.yaml#/definitions/flag
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++ description:
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++ Ignore power-on pin strapping to configure LED open-drain or EEPROM
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++ presence. This is needed for devices with incorrect configuration or when
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++ the OEM has decided not to use pin strapping and falls back to SW regs.
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++
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++ qca,led-open-drain:
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++ $ref: /schemas/types.yaml#/definitions/flag
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++ description:
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++ Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
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++ be set, otherwise the driver will fail at probe. This is required if the
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++ OEM does not use pin strapping to set this mode and prefers to set it
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++ using SW regs. The pin strappings related to LED open-drain mode are
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++ B68 on the QCA832x and B49 on the QCA833x.
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++
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++ mdio:
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++ type: object
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++ description: Qca8k switch have an internal mdio to access switch port.
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++ If this is not present, the legacy mapping is used and the
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++ internal mdio access is used.
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++ With the legacy mapping the reg corresponding to the internal
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++ mdio is the switch reg with an offset of -1.
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++
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++ properties:
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++ '#address-cells':
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++ const: 1
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++ '#size-cells':
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++ const: 0
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++
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++ patternProperties:
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++ "^(ethernet-)?phy@[0-4]$":
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++ type: object
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++
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++ allOf:
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++ - $ref: "http://devicetree.org/schemas/net/mdio.yaml#"
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++
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++ properties:
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++ reg:
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++ maxItems: 1
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++
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++ required:
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++ - reg
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++
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++patternProperties:
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++ "^(ethernet-)?ports$":
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++ type: object
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++ properties:
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++ '#address-cells':
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++ const: 1
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++ '#size-cells':
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++ const: 0
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++
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++ patternProperties:
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++ "^(ethernet-)?port@[0-6]$":
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++ type: object
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++ description: Ethernet switch ports
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++
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++ properties:
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++ reg:
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++ description: Port number
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++
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++ label:
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++ description:
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++ Describes the label associated with this port, which will become
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++ the netdev name
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++ $ref: /schemas/types.yaml#/definitions/string
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++
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++ link:
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++ description:
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++ Should be a list of phandles to other switch's DSA port. This
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++ port is used as the outgoing port towards the phandle ports. The
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++ full routing information must be given, not just the one hop
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++ routes to neighbouring switches
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++ $ref: /schemas/types.yaml#/definitions/phandle-array
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++
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++ ethernet:
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++ description:
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++ Should be a phandle to a valid Ethernet device node. This host
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++ device is what the switch port is connected to
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++ $ref: /schemas/types.yaml#/definitions/phandle
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++
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++ phy-handle: true
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++
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++ phy-mode: true
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++
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++ fixed-link: true
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++
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++ mac-address: true
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++
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++ sfp: true
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++
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++ qca,sgmii-rxclk-falling-edge:
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++ $ref: /schemas/types.yaml#/definitions/flag
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++ description:
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++ Set the receive clock phase to falling edge. Mostly commonly used on
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++ the QCA8327 with CPU port 0 set to SGMII.
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++
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++ qca,sgmii-txclk-falling-edge:
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++ $ref: /schemas/types.yaml#/definitions/flag
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++ description:
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++ Set the transmit clock phase to falling edge.
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++
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++ qca,sgmii-enable-pll:
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++ $ref: /schemas/types.yaml#/definitions/flag
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++ description:
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++ For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
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++ Signal Detection. On the QCA8327 this should not be enabled, otherwise
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++ the SGMII port will not initialize. When used on the QCA8337, revision 3
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++ or greater, a warning will be displayed. When the CPU port is set to
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++ SGMII on the QCA8337, it is advised to set this unless a communication
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++ issue is observed.
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++
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++ required:
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++ - reg
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++
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++ additionalProperties: false
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++
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++oneOf:
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++ - required:
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++ - ports
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++ - required:
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++ - ethernet-ports
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++
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++required:
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++ - compatible
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++ - reg
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++
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++additionalProperties: true
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++
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++examples:
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++ - |
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++ #include <dt-bindings/gpio/gpio.h>
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++
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++ mdio {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ external_phy_port1: ethernet-phy@0 {
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++ reg = <0>;
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++ };
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++
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++ external_phy_port2: ethernet-phy@1 {
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++ reg = <1>;
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++ };
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++
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++ external_phy_port3: ethernet-phy@2 {
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++ reg = <2>;
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++ };
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++
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++ external_phy_port4: ethernet-phy@3 {
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++ reg = <3>;
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++ };
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++
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++ external_phy_port5: ethernet-phy@4 {
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++ reg = <4>;
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++ };
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++
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++ switch@10 {
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++ compatible = "qca,qca8337";
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
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++ reg = <0x10>;
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++
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++ ports {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ port@0 {
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++ reg = <0>;
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++ label = "cpu";
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++ ethernet = <&gmac1>;
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++ phy-mode = "rgmii";
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++
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++ fixed-link {
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++ speed = <1000>;
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++ full-duplex;
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++ };
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++ };
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++
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++ port@1 {
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|
++ reg = <1>;
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++ label = "lan1";
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++ phy-handle = <&external_phy_port1>;
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|
++ };
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++
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|
|
++ port@2 {
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|
++ reg = <2>;
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|
++ label = "lan2";
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|
++ phy-handle = <&external_phy_port2>;
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|
|
++ };
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|
|
++
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|
|
++ port@3 {
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|
|
++ reg = <3>;
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|
++ label = "lan3";
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|
|
++ phy-handle = <&external_phy_port3>;
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|
|
++ };
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|
++
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|
|
++ port@4 {
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|
|
++ reg = <4>;
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|
|
++ label = "lan4";
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|
|
++ phy-handle = <&external_phy_port4>;
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|
|
++ };
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|
|
++
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|
|
++ port@5 {
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|
|
++ reg = <5>;
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|
|
++ label = "wan";
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|
|
++ phy-handle = <&external_phy_port5>;
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|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++ - |
|
|
|
++ #include <dt-bindings/gpio/gpio.h>
|
|
|
++
|
|
|
++ mdio {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ switch@10 {
|
|
|
++ compatible = "qca,qca8337";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
|
|
++ reg = <0x10>;
|
|
|
++
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|
|
++ ports {
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|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
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|
|
++ port@0 {
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|
|
++ reg = <0>;
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|
|
++ label = "cpu";
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|
|
++ ethernet = <&gmac1>;
|
|
|
++ phy-mode = "rgmii";
|
|
|
++
|
|
|
++ fixed-link {
|
|
|
++ speed = <1000>;
|
|
|
++ full-duplex;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ port@1 {
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|
|
++ reg = <1>;
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|
|
++ label = "lan1";
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|
|
++ phy-mode = "internal";
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|
|
++ phy-handle = <&internal_phy_port1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ port@2 {
|
|
|
++ reg = <2>;
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|
|
++ label = "lan2";
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|
|
++ phy-mode = "internal";
|
|
|
++ phy-handle = <&internal_phy_port2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ port@3 {
|
|
|
++ reg = <3>;
|
|
|
++ label = "lan3";
|
|
|
++ phy-mode = "internal";
|
|
|
++ phy-handle = <&internal_phy_port3>;
|
|
|
++ };
|
|
|
++
|
|
|
++ port@4 {
|
|
|
++ reg = <4>;
|
|
|
++ label = "lan4";
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|
|
++ phy-mode = "internal";
|
|
|
++ phy-handle = <&internal_phy_port4>;
|
|
|
++ };
|
|
|
++
|
|
|
++ port@5 {
|
|
|
++ reg = <5>;
|
|
|
++ label = "wan";
|
|
|
++ phy-mode = "internal";
|
|
|
++ phy-handle = <&internal_phy_port5>;
|
|
|
++ };
|
|
|
++
|
|
|
++ port@6 {
|
|
|
++ reg = <0>;
|
|
|
++ label = "cpu";
|
|
|
++ ethernet = <&gmac1>;
|
|
|
++ phy-mode = "sgmii";
|
|
|
++
|
|
|
++ qca,sgmii-rxclk-falling-edge;
|
|
|
++
|
|
|
++ fixed-link {
|
|
|
++ speed = <1000>;
|
|
|
++ full-duplex;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ mdio {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ internal_phy_port1: ethernet-phy@0 {
|
|
|
++ reg = <0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ internal_phy_port2: ethernet-phy@1 {
|
|
|
++ reg = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ internal_phy_port3: ethernet-phy@2 {
|
|
|
++ reg = <2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ internal_phy_port4: ethernet-phy@3 {
|
|
|
++ reg = <3>;
|
|
|
++ };
|
|
|
++
|
|
|
++ internal_phy_port5: ethernet-phy@4 {
|
|
|
++ reg = <4>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
Matthew Hagan