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@@ -235,9 +235,9 @@ static inline u32 ar71xx_gpio_rr(unsigned reg)
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return __raw_readl(ar71xx_gpio_base + reg);
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}
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-extern void ar71xx_gpio_init(void) __init;
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-extern void ar71xx_gpio_function_enable(u32 mask);
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-extern void ar71xx_gpio_function_disable(u32 mask);
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+void ar71xx_gpio_init(void) __init;
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+void ar71xx_gpio_function_enable(u32 mask);
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+void ar71xx_gpio_function_disable(u32 mask);
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/*
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* DDR_CTRL block
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@@ -281,7 +281,7 @@ static inline u32 ar71xx_ddr_rr(unsigned reg)
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return __raw_readl(ar71xx_ddr_base + reg);
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}
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-extern void ar71xx_ddr_flush(u32 reg);
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+void ar71xx_ddr_flush(u32 reg);
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/*
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* PCI block
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@@ -396,8 +396,8 @@ static inline u32 ar71xx_reset_rr(unsigned reg)
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return __raw_readl(ar71xx_reset_base + reg);
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}
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-extern void ar71xx_device_stop(u32 mask);
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-extern void ar71xx_device_start(u32 mask);
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+void ar71xx_device_stop(u32 mask);
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+void ar71xx_device_start(u32 mask);
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/*
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* SPI block
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