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@@ -13,7 +13,7 @@
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/* ============================= */
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--- a/src/drv_vmmc_bbd.c
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+++ b/src/drv_vmmc_bbd.c
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-@@ -939,7 +939,11 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
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+@@ -1072,7 +1072,11 @@
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IFX_uint8_t padBytes = 0;
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#endif
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IFX_uint16_t cram_offset, cram_crc,
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@@ -28,59 +28,13 @@
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cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t));
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--- a/src/drv_vmmc_danube.h
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+++ b/src/drv_vmmc_danube.h
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-@@ -15,12 +15,59 @@
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+@@ -15,56 +15,18 @@
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*/
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#if defined SYSTEM_DANUBE
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-#include <asm/ifx/ifx_gpio.h>
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-+# if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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-+# include <asm/mach-ifxmips/ifxmips_gpio.h>
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++#include <xway/xway.h>
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+
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-+# define IFX_GPIO_PIN_NUMBER_PER_PORT 16
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-+# define IFX_GPIO_PIN_ID(port, pin) ((port) \
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-+ * IFX_GPIO_PIN_NUMBER_PER_PORT \
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-+ + (pin))
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-+# define IFX_GPIO_PIN_ID_TO_PORT(pin_id) (pin_id >> 4)
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-+# define IFX_GPIO_PIN_ID_TO_PIN(pin_id) (pin_id & 0x0F)
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-+
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-+# define IFX_GPIO_MODULE_TAPI_VMMC 0 /* not used */
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-+
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-+# define ifx_gpio_pin_reserve(a,b) 0 /* obsolete */
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-+
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-+# define ifx_gpio_open_drain_set(a,b) ifxmips_port_set_open_drain( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+
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-+# define ifx_gpio_altsel0_set(a,b) ifxmips_port_set_altsel0( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+
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-+# define ifx_gpio_altsel1_set(a,b) ifxmips_port_set_altsel1( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+
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-+# define ifx_gpio_altsel0_clear(a,b) ifxmips_port_clear_altsel0( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+
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-+# define ifx_gpio_altsel1_clear(a,b) ifxmips_port_clear_altsel1( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+
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-+# define ifx_gpio_dir_in_set(a,b) ifxmips_port_set_dir_in( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+
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-+# define ifx_gpio_dir_out_set(a,b) ifxmips_port_set_dir_out( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+
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-+# define ifx_gpio_pin_free(a,b) ifxmips_port_free_pin( \
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-+ IFX_GPIO_PIN_ID_TO_PORT(a), \
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-+ IFX_GPIO_PIN_ID_TO_PIN(a))
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-+# else
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-+# include <asm/ifx/ifx_gpio.h>
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-+# endif
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#else
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#error no system selected
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#endif
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@@ -90,11 +44,67 @@
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/**
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*/
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+ #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
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+ do { \
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+- ret = VMMC_statusOk; \
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+- /* Reserve P0.0 as TDM/FSC */ \
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+- if (!GPIOreserved) \
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+- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
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+- \
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+- /* Reserve P1.9 as TDM/DO */ \
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+- if (!GPIOreserved) \
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+- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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+- \
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+- /* Reserve P1.10 as TDM/DI */ \
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+- if (!GPIOreserved) \
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+- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\
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+- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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+- \
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+- /* Reserve P1.11 as TDM/DCL */ \
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+- if (!GPIOreserved) \
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+- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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+- \
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+- if (mode == 2) { \
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+- /* TDM/FSC+DCL Master */ \
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+- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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+- } else { \
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+- /* TDM/FSC+DCL Slave */ \
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+- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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+- } \
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+ } while(0);
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+
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+ /**
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+@@ -72,11 +34,6 @@
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+ */
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+ #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
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+ do { \
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+- ret = VMMC_statusOk; \
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+- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
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+- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
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+ } while (0)
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+
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+ #endif /* _DRV_VMMC_AMAZON_S_H */
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--- a/src/drv_vmmc_init.c
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+++ b/src/drv_vmmc_init.c
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-@@ -48,6 +48,14 @@
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- #include "drv_vmmc_pmc.h"
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- #endif /* PMC_SUPPORTED */
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+@@ -52,6 +52,14 @@
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+ #include "ifx_pmu.h"
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+ #endif /* PMU_SUPPORTED */
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
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@@ -123,21 +133,29 @@
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/* ============================= */
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--- a/src/mps/drv_mps_vmmc_common.c
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+++ b/src/mps/drv_mps_vmmc_common.c
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-@@ -35,8 +35,35 @@
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+@@ -17,6 +17,7 @@
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+ /* Includes */
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+ /* ============================= */
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+ #include "drv_config.h"
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++#include "drv_vmmc_init.h"
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+
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+ #undef USE_PLAIN_VOICE_FIRMWARE
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+ #undef PRINT_ON_ERR_INTERRUPT
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+@@ -35,8 +36,35 @@
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#include "ifxos_interrupt.h"
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#include "ifxos_time.h"
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx/ifx_gptu.h>
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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-+# include <asm/mach-ifxmips/ifxmips.h>
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-+# include <asm/mach-ifxmips/ifxmips_irq.h>
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-+# include <asm/mach-ifxmips/ifxmips_gptu.h>
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++# include <lantiq.h>
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++# include <irq.h>
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++# include <lantiq_timer.h>
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+
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-+# define ifx_gptu_timer_request ifxmips_request_timer
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-+# define ifx_gptu_timer_start ifxmips_start_timer
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-+# define ifx_gptu_countvalue_get ifxmips_get_count_value
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-+# define ifx_gptu_timer_free ifxmips_free_timer
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++# define ifx_gptu_timer_request lq_request_timer
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++# define ifx_gptu_timer_start lq_start_timer
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++# define ifx_gptu_countvalue_get lq_get_count_value
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++# define ifx_gptu_timer_free lq_free_timer
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+
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+# define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
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+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
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@@ -153,7 +171,7 @@
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+
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+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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+
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-+# define bsp_mask_and_ack_irq ifxmips_mask_and_ack_irq
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++# define bsp_mask_and_ack_irq lq_mask_and_ack_irq
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+#else
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+# include <asm/ifx/ifx_regs.h>
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+# include <asm/ifx/ifx_gptu.h>
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@@ -161,7 +179,7 @@
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#include "drv_mps_vmmc.h"
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#include "drv_mps_vmmc_dbg.h"
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-@@ -193,7 +220,8 @@ IFX_boolean_t ifx_mps_ext_bufman ()
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+@@ -201,7 +229,8 @@
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*/
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IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
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{
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@@ -171,21 +189,7 @@
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IFX_int32_t index = fastbuf_index;
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if (fastbuf_initialized == 0)
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-@@ -219,11 +247,11 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_
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- if ((volatile IFX_uint32_t) fastbuf_pool[index] & FASTBUF_USED)
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- continue;
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- ptr = fastbuf_pool[index];
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-- (volatile IFX_uint32_t) fastbuf_pool[index] |= FASTBUF_USED;
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-+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] | FASTBUF_USED;
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- if ((priority == FASTBUF_FW_OWNED) || (priority == FASTBUF_CMD_OWNED) ||
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- (priority == FASTBUF_EVENT_OWNED) ||
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- (priority == FASTBUF_WRITE_OWNED))
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-- (volatile IFX_uint32_t) fastbuf_pool[index] |= priority;
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-+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] | priority;
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- fastbuf_index = index;
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- IFXOS_UNLOCKINT (flags);
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- return (IFX_void_t *) ptr;
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-@@ -247,7 +275,7 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_
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+@@ -255,7 +284,7 @@
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*/
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IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
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{
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@@ -194,19 +198,7 @@
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IFX_int32_t index = fastbuf_index;
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IFXOS_LOCKINT (flags);
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-@@ -261,8 +289,9 @@ IFX_void_t ifx_mps_fastbuf_free (const I
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- FASTBUF_EVENT_OWNED | FASTBUF_WRITE_OWNED))
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- == ((IFX_uint32_t) ptr | FASTBUF_USED))
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- {
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-- (volatile IFX_uint32_t) fastbuf_pool[index] &= ~FASTBUF_USED;
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-- (volatile IFX_uint32_t) fastbuf_pool[index] &=
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-+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] & ~FASTBUF_USED;
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-+
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-+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] &
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- ~(FASTBUF_FW_OWNED | FASTBUF_CMD_OWNED | FASTBUF_EVENT_OWNED |
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- FASTBUF_WRITE_OWNED);
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- IFXOS_UNLOCKINT (flags);
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-@@ -444,7 +473,7 @@ static mps_buffer_state_e ifx_mps_bufman
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+@@ -451,7 +480,7 @@
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*/
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static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
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{
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@@ -215,7 +207,7 @@
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if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
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{
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-@@ -471,7 +500,7 @@ static IFX_int32_t ifx_mps_bufman_inc_le
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+@@ -478,7 +507,7 @@
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*/
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static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
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{
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@@ -224,7 +216,7 @@
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if (mps_buffer.buf_level < value)
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{
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-@@ -932,7 +961,7 @@ IFX_int32_t ifx_mps_common_open (mps_com
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+@@ -946,7 +975,7 @@
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mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
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IFX_boolean_t from_kernel)
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{
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@@ -233,7 +225,7 @@
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IFXOS_LOCKINT (flags);
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-@@ -1048,7 +1077,7 @@ IFX_int32_t ifx_mps_common_close (mps_mb
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+@@ -1062,7 +1091,7 @@
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IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
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{
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IFX_int32_t count;
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@@ -242,7 +234,7 @@
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IFXOS_LOCKINT (flags);
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IFXOS_BlockFree (pFW_img_data);
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-@@ -1544,7 +1573,7 @@ IFX_int32_t ifx_mps_mbx_read_message (mp
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+@@ -1558,7 +1587,7 @@
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IFX_uint32_t * bytes)
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{
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IFX_int32_t i, ret;
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@@ -251,7 +243,7 @@
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IFXOS_LOCKINT (flags);
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-@@ -1751,7 +1780,7 @@ IFX_int32_t ifx_mps_mbx_write_message (m
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+@@ -1768,7 +1797,7 @@
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{
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mps_fifo *mbx;
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IFX_uint32_t i;
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@@ -260,7 +252,7 @@
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IFX_int32_t retval = -EAGAIN;
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IFX_int32_t retries = 0;
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IFX_uint32_t word = 0;
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-@@ -2138,6 +2167,7 @@ IFX_int32_t ifx_mps_mbx_write_cmd (mps_m
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+@@ -2163,6 +2192,7 @@
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TRACE (MPS, DBG_LEVEL_HIGH,
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("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
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}
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@@ -268,7 +260,7 @@
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return retval;
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}
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-@@ -2161,7 +2191,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
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+@@ -2186,7 +2216,7 @@
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mps_mbx_dev *mbx_dev;
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MbxMsg_s msg;
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IFX_uint32_t bytes_read = 0;
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@@ -277,7 +269,7 @@
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IFX_int32_t ret;
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/* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
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-@@ -2252,7 +2282,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
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+@@ -2277,7 +2307,7 @@
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{
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ifx_mps_bufman_dec_level (1);
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if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
|
|
@@ -286,7 +278,7 @@
|
|
|
{
|
|
|
IFXOS_LockRelease (pMPSDev->provide_buffer);
|
|
|
}
|
|
|
-@@ -2295,7 +2325,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
|
|
|
+@@ -2320,7 +2350,7 @@
|
|
|
#endif /* CONFIG_PROC_FS */
|
|
|
ifx_mps_bufman_dec_level (1);
|
|
|
if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
|
|
@@ -295,7 +287,7 @@
|
|
|
{
|
|
|
IFXOS_LockRelease (pMPSDev->provide_buffer);
|
|
|
}
|
|
|
-@@ -2325,7 +2355,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
|
|
|
+@@ -2350,7 +2380,7 @@
|
|
|
IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
|
|
|
{
|
|
|
mps_fifo *mbx;
|
|
@@ -304,7 +296,7 @@
|
|
|
|
|
|
/* set pointer to upstream command mailbox */
|
|
|
mbx = &(pMPSDev->cmd_upstrm_fifo);
|
|
|
-@@ -2373,7 +2403,7 @@ IFX_void_t ifx_mps_mbx_event_upstream (I
|
|
|
+@@ -2398,7 +2428,7 @@
|
|
|
mps_event_msg msg;
|
|
|
IFX_int32_t length = 0;
|
|
|
IFX_int32_t read_length = 0;
|
|
@@ -313,7 +305,7 @@
|
|
|
|
|
|
/* set pointer to upstream event mailbox */
|
|
|
mbx = &(pMPSDev->event_upstrm_fifo);
|
|
|
-@@ -2616,7 +2646,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (
|
|
|
+@@ -2641,7 +2671,7 @@
|
|
|
*/
|
|
|
IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
|
|
|
{
|
|
@@ -322,7 +314,7 @@
|
|
|
MPS_Ad0Reg_u Ad0Reg;
|
|
|
|
|
|
IFXOS_LOCKINT (flags);
|
|
|
-@@ -2642,7 +2672,7 @@ IFX_void_t ifx_mps_dd_mbx_int_enable (IF
|
|
|
+@@ -2667,7 +2697,7 @@
|
|
|
*/
|
|
|
IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
|
|
|
{
|
|
@@ -331,7 +323,7 @@
|
|
|
MPS_Ad0Reg_u Ad0Reg;
|
|
|
|
|
|
IFXOS_LOCKINT (flags);
|
|
|
-@@ -2769,6 +2799,7 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
|
|
|
+@@ -2794,6 +2824,7 @@
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -339,7 +331,7 @@
|
|
|
if (MPS_Ad0StatusReg.fld.du_mbx)
|
|
|
{
|
|
|
#ifdef CONFIG_PROC_FS
|
|
|
-@@ -3062,7 +3093,8 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_
|
|
|
+@@ -3087,7 +3118,8 @@
|
|
|
*/
|
|
|
IFX_return_t ifx_mps_init_gpt ()
|
|
|
{
|
|
@@ -351,7 +343,7 @@
|
|
|
timer = TIMER1A;
|
|
|
--- a/src/mps/drv_mps_vmmc_danube.c
|
|
|
+++ b/src/mps/drv_mps_vmmc_danube.c
|
|
|
-@@ -32,9 +32,20 @@
|
|
|
+@@ -32,9 +32,21 @@
|
|
|
#include "ifxos_select.h"
|
|
|
#include "ifxos_interrupt.h"
|
|
|
|
|
@@ -359,14 +351,15 @@
|
|
|
-#include <asm/ifx/ifx_gpio.h>
|
|
|
-#include <asm/ifx/common_routines.h>
|
|
|
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
|
|
|
-+# include <asm/mach-ifxmips/ifxmips.h>
|
|
|
-+# include <asm/mach-ifxmips/ifxmips_irq.h>
|
|
|
-+# include <asm/mach-ifxmips/ifxmips_gptu.h>
|
|
|
-+# include <asm/mach-ifxmips/ifxmips_prom.h>
|
|
|
++# include <lantiq.h>
|
|
|
++# include <irq.h>
|
|
|
++# include <lantiq_timer.h>
|
|
|
+# include <linux/dma-mapping.h>
|
|
|
+
|
|
|
-+# define IFX_RCU_RST_REQ IFXMIPS_RCU_RST
|
|
|
-+# define IFX_RCU_RST_REQ_CPU1 IFXMIPS_RCU_RST_CPU1
|
|
|
++
|
|
|
++# define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
|
|
|
++#define IFX_RCU_RST_REQ_CPU1 (1 << 3)
|
|
|
++# define IFX_RCU_RST_REQ LQ_RCU_RST
|
|
|
+#else
|
|
|
+# include <asm/ifx/ifx_regs.h>
|
|
|
+# include <asm/ifx_vpe.h>
|
|
@@ -375,7 +368,7 @@
|
|
|
|
|
|
#include "drv_mps_vmmc.h"
|
|
|
#include "drv_mps_vmmc_dbg.h"
|
|
|
-@@ -72,6 +71,23 @@ volatile IFX_uint32_t *danube_cp1_base;
|
|
|
+@@ -71,6 +83,20 @@
|
|
|
/* Local function definition */
|
|
|
/* ============================= */
|
|
|
|
|
@@ -385,21 +378,18 @@
|
|
|
+ return 2;
|
|
|
+}
|
|
|
+
|
|
|
++unsigned int *lq_get_cp1_base(void);
|
|
|
++
|
|
|
+IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)
|
|
|
+{
|
|
|
-+ if (!danube_cp1_base) {
|
|
|
-+ dma_addr_t dma;
|
|
|
-+ danube_cp1_base = dma_alloc_coherent(NULL, ifx_get_cp1_size()<<20, &dma, GFP_ATOMIC);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ return (IFX_uint32_t*)danube_cp1_base;
|
|
|
++ return lq_get_cp1_base();
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
/******************************************************************************
|
|
|
* DANUBE Specific Routines
|
|
|
******************************************************************************/
|
|
|
-@@ -119,6 +132,15 @@ IFX_int32_t ifx_mps_download_firmware (m
|
|
|
+@@ -130,6 +156,15 @@
|
|
|
}
|
|
|
|
|
|
/* check if FW image fits in available memory space */
|
|
@@ -415,7 +405,7 @@
|
|
|
if (mem > ifx_get_cp1_size())
|
|
|
{
|
|
|
TRACE (MPS, DBG_LEVEL_HIGH,
|
|
|
-@@ -126,6 +148,7 @@ IFX_int32_t ifx_mps_download_firmware (m
|
|
|
+@@ -137,6 +172,7 @@
|
|
|
__FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
|
|
|
return IFX_ERROR;
|
|
|
}
|
|
@@ -423,7 +413,7 @@
|
|
|
|
|
|
/* reset the driver */
|
|
|
ifx_mps_reset ();
|
|
|
-@@ -337,7 +360,7 @@ IFX_void_t ifx_mps_release (IFX_void_t)
|
|
|
+@@ -357,7 +393,7 @@
|
|
|
*/
|
|
|
IFX_void_t ifx_mps_wdog_expiry()
|
|
|
{
|
|
@@ -441,9 +431,9 @@
|
|
|
-#include <asm/ifx/ifx_regs.h>
|
|
|
-#include <asm/ifx_vpe.h>
|
|
|
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
|
|
|
-+# include <asm/mach-ifxmips/ifxmips.h>
|
|
|
-+# include <asm/mach-ifxmips/ifxmips_irq.h>
|
|
|
-+# include <asm/mach-ifxmips/ifxmips_gpio.h>
|
|
|
++# include <lantiq.h>
|
|
|
++# include <irq.h>
|
|
|
++# include <xway/xway.h>
|
|
|
+# include <gpio.h>
|
|
|
+#else
|
|
|
+# include <asm/ifx/ifx_regs.h>
|
|
@@ -454,7 +444,7 @@
|
|
|
/* MPS Common defines */
|
|
|
--- a/src/mps/drv_mps_vmmc_linux.c
|
|
|
+++ b/src/mps/drv_mps_vmmc_linux.c
|
|
|
-@@ -40,10 +40,26 @@
|
|
|
+@@ -40,10 +40,28 @@
|
|
|
#include <linux/moduleparam.h>
|
|
|
#endif /* */
|
|
|
|
|
@@ -463,8 +453,9 @@
|
|
|
-#include <asm/ifx/ifx_regs.h>
|
|
|
-#include <asm/ifx_vpe.h>
|
|
|
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
|
|
|
-+# include <asm/mach-ifxmips/ifxmips.h>
|
|
|
-+# include <asm/mach-ifxmips/ifxmips_irq.h>
|
|
|
++#include "drv_vmmc_init.h"
|
|
|
++# include <lantiq.h>
|
|
|
++# include <irq.h>
|
|
|
+
|
|
|
+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
|
|
|
+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
|
|
@@ -476,7 +467,8 @@
|
|
|
+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
|
|
|
+# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
|
|
|
+# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
|
|
|
-+# define IFX_ICU_IM4_IER IFXMIPS_ICU_IM4_IER
|
|
|
++#define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
|
|
|
++# define IFX_ICU_IM4_IER (LQ_ICU_BASE_ADDR + 0x00A8)
|
|
|
+#else
|
|
|
+# include <asm/ifx/irq.h>
|
|
|
+# include <asm/ifx/ifx_regs.h>
|
|
@@ -485,16 +477,16 @@
|
|
|
|
|
|
/* lib_ifxos headers */
|
|
|
#include "ifx_types.h"
|
|
|
-@@ -914,7 +930,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode
|
|
|
+@@ -915,7 +933,7 @@
|
|
|
#endif /* MPS_FIFO_BLOCKING_WRITE */
|
|
|
case FIO_MPS_GET_STATUS:
|
|
|
{
|
|
|
- IFX_uint32_t flags;
|
|
|
+ unsigned long flags;
|
|
|
|
|
|
- IFXOS_LOCKINT (flags);
|
|
|
-
|
|
|
-@@ -949,7 +965,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode
|
|
|
+ /* get the status of the channel */
|
|
|
+ if (!from_kernel)
|
|
|
+@@ -949,7 +967,7 @@
|
|
|
#if CONFIG_MPS_HISTORY_SIZE > 0
|
|
|
case FIO_MPS_GET_CMD_HISTORY:
|
|
|
{
|
|
@@ -503,7 +495,7 @@
|
|
|
|
|
|
if (from_kernel)
|
|
|
{
|
|
|
-@@ -1637,6 +1653,7 @@ IFX_int32_t ifx_mps_get_status_proc (IFX
|
|
|
+@@ -1641,6 +1659,7 @@
|
|
|
sprintf (buf + len, " minLv: \t %8d\n",
|
|
|
ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
|
|
|
}
|
|
@@ -511,3 +503,57 @@
|
|
|
return len;
|
|
|
}
|
|
|
|
|
|
+--- a/src/drv_vmmc_init.h
|
|
|
++++ b/src/drv_vmmc_init.h
|
|
|
+@@ -53,4 +53,41 @@
|
|
|
+ extern IFX_int32_t VMMC_DeviceDriverStart(IFX_void_t);
|
|
|
+ extern IFX_void_t VMMC_DeviceDriverStop(IFX_void_t);
|
|
|
+
|
|
|
++
|
|
|
++#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
|
|
|
++#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
|
|
|
++
|
|
|
++#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
|
|
|
++#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
|
|
|
++#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
|
|
|
++#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
|
|
|
++#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
|
|
|
++#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
|
|
|
++#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
|
|
|
++#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
|
|
|
++#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
|
|
|
++#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
|
|
|
++#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
|
|
|
++#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
|
|
|
++#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
|
|
|
++#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
|
|
|
++#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
|
|
|
++#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
|
|
|
++#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
|
|
|
++#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
|
|
|
++#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
|
|
|
++#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
|
|
|
++#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
|
|
|
++#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
|
|
|
++#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
|
|
|
++#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
|
|
|
++#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
|
|
|
++
|
|
|
++#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
|
|
|
++#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28)
|
|
|
++#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
|
|
|
++#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)
|
|
|
++#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
|
|
|
++#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)
|
|
|
++
|
|
|
+ #endif /* _DRV_VMMC_INIT_H */
|
|
|
+--- a/src/drv_vmmc_ioctl.c
|
|
|
++++ b/src/drv_vmmc_ioctl.c
|
|
|
+@@ -18,6 +18,7 @@
|
|
|
+ /* Includes */
|
|
|
+ /* ============================= */
|
|
|
+ #include "drv_api.h"
|
|
|
++#include "drv_vmmc_init.h"
|
|
|
+ #include "drv_vmmc_api.h"
|
|
|
+ #include "drv_vmmc_bbd.h"
|
|
|
+
|