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@@ -37,7 +37,6 @@
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#define MT6575_SD_H
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#include <linux/bitops.h>
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-#include <linux/interrupt.h>
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#include <linux/mmc/host.h>
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// #include <mach/mt6575_reg_base.h> /* --- by chhung */
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@@ -45,7 +44,7 @@
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/*--------------------------------------------------------------------------*/
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/* Common Macro */
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/*--------------------------------------------------------------------------*/
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-#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
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+#define REG_ADDR(x) (base + OFFSET_##x)
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/*--------------------------------------------------------------------------*/
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/* Common Definition */
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@@ -89,15 +88,15 @@
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#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
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enum {
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- RESP_NONE = 0,
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- RESP_R1,
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- RESP_R2,
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- RESP_R3,
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- RESP_R4,
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- RESP_R5,
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- RESP_R6,
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- RESP_R7,
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- RESP_R1B
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+ RESP_NONE = 0,
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+ RESP_R1,
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+ RESP_R2,
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+ RESP_R3,
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+ RESP_R4,
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+ RESP_R5,
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+ RESP_R6,
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+ RESP_R7,
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+ RESP_R1B
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};
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/*--------------------------------------------------------------------------*/
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@@ -254,7 +253,7 @@ enum {
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#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
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#define MSDC_PS_DAT (0xff << 16) /* R */
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#define MSDC_PS_CMD (0x1 << 24) /* R */
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-#define MSDC_PS_WP (0x1UL<< 31) /* R */
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+#define MSDC_PS_WP (0x1UL << 31) /* R */
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/* MSDC_INT mask */
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#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
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@@ -295,14 +294,14 @@ enum {
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/* MSDC_FIFOCS mask */
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#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
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#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
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-#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
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+#define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */
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/* SDC_CFG mask */
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#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
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#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
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#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
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#define SDC_CFG_SDIO (0x1 << 19) /* RW */
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-#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
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+#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
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#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
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#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
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@@ -315,7 +314,7 @@ enum {
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#define SDC_CMD_RW (0x1 << 13) /* RW */
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#define SDC_CMD_STOP (0x1 << 14) /* RW */
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#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
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-#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
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+#define SDC_CMD_BLKLEN (0xfff << 16) /* RW */
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#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
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#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
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@@ -397,7 +396,7 @@ enum {
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#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
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#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
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#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
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-#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
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+#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */
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/* MSDC_PAD_CTL1 mask */
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#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
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@@ -408,7 +407,7 @@ enum {
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#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
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#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
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#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
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-#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
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+#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */
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/* MSDC_PAD_CTL2 mask */
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#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
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@@ -419,7 +418,7 @@ enum {
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#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
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#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
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#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
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-#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
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+#define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */
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/* MSDC_PAD_TUNE mask */
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#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
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@@ -439,564 +438,549 @@ enum {
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#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
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#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
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-#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
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-#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
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-#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
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-#define CARD_READY_FOR_DATA (1<<8)
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-#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
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+#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10)
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+#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
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+#define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6)
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+#define CARD_READY_FOR_DATA (1 << 8)
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+#define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)
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/*--------------------------------------------------------------------------*/
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/* Descriptor Structure */
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/*--------------------------------------------------------------------------*/
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-typedef struct {
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- u32 hwo:1; /* could be changed by hw */
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- u32 bdp:1;
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- u32 rsv0:6;
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- u32 chksum:8;
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- u32 intr:1;
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- u32 rsv1:15;
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- void *next;
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- void *ptr;
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- u32 buflen:16;
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- u32 extlen:8;
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- u32 rsv2:8;
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- u32 arg;
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- u32 blknum;
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- u32 cmd;
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-} gpd_t;
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-
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-typedef struct {
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- u32 eol:1;
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- u32 rsv0:7;
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- u32 chksum:8;
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- u32 rsv1:1;
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- u32 blkpad:1;
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- u32 dwpad:1;
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- u32 rsv2:13;
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- void *next;
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- void *ptr;
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- u32 buflen:16;
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- u32 rsv3:16;
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-} bd_t;
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+struct gpd {
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+ u32 hwo:1; /* could be changed by hw */
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+ u32 bdp:1;
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+ u32 rsv0:6;
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+ u32 chksum:8;
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+ u32 intr:1;
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+ u32 rsv1:15;
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+ void *next;
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+ void *ptr;
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+ u32 buflen:16;
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+ u32 extlen:8;
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+ u32 rsv2:8;
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+ u32 arg;
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+ u32 blknum;
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+ u32 cmd;
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+};
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+
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+struct bd {
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+ u32 eol:1;
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+ u32 rsv0:7;
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+ u32 chksum:8;
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+ u32 rsv1:1;
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+ u32 blkpad:1;
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+ u32 dwpad:1;
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+ u32 rsv2:13;
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+ void *next;
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+ void *ptr;
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+ u32 buflen:16;
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+ u32 rsv3:16;
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+};
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/*--------------------------------------------------------------------------*/
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/* Register Debugging Structure */
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/*--------------------------------------------------------------------------*/
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-typedef struct {
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- u32 msdc:1;
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- u32 ckpwn:1;
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- u32 rst:1;
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- u32 pio:1;
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- u32 ckdrven:1;
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- u32 start18v:1;
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- u32 pass18v:1;
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- u32 ckstb:1;
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- u32 ckdiv:8;
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- u32 ckmod:2;
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- u32 pad:14;
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-} msdc_cfg_reg;
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-typedef struct {
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- u32 sdr104cksel:1;
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- u32 rsmpl:1;
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- u32 dsmpl:1;
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- u32 ddlysel:1;
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- u32 ddr50ckd:1;
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- u32 dsplsel:1;
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- u32 pad1:10;
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- u32 d0spl:1;
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- u32 d1spl:1;
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- u32 d2spl:1;
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- u32 d3spl:1;
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- u32 d4spl:1;
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- u32 d5spl:1;
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- u32 d6spl:1;
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- u32 d7spl:1;
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- u32 riscsz:1;
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- u32 pad2:7;
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-} msdc_iocon_reg;
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-typedef struct {
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- u32 cden:1;
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- u32 cdsts:1;
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- u32 pad1:10;
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- u32 cddebounce:4;
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- u32 dat:8;
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- u32 cmd:1;
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- u32 pad2:6;
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- u32 wp:1;
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-} msdc_ps_reg;
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-typedef struct {
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- u32 mmcirq:1;
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- u32 cdsc:1;
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- u32 pad1:1;
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- u32 atocmdrdy:1;
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- u32 atocmdtmo:1;
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- u32 atocmdcrc:1;
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- u32 dmaqempty:1;
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- u32 sdioirq:1;
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- u32 cmdrdy:1;
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- u32 cmdtmo:1;
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- u32 rspcrc:1;
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- u32 csta:1;
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- u32 xfercomp:1;
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- u32 dxferdone:1;
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- u32 dattmo:1;
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- u32 datcrc:1;
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- u32 atocmd19done:1;
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- u32 pad2:15;
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-} msdc_int_reg;
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-typedef struct {
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- u32 mmcirq:1;
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- u32 cdsc:1;
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- u32 pad1:1;
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- u32 atocmdrdy:1;
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- u32 atocmdtmo:1;
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- u32 atocmdcrc:1;
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- u32 dmaqempty:1;
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- u32 sdioirq:1;
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- u32 cmdrdy:1;
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- u32 cmdtmo:1;
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- u32 rspcrc:1;
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- u32 csta:1;
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- u32 xfercomp:1;
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- u32 dxferdone:1;
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- u32 dattmo:1;
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- u32 datcrc:1;
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- u32 atocmd19done:1;
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- u32 pad2:15;
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-} msdc_inten_reg;
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-typedef struct {
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- u32 rxcnt:8;
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- u32 pad1:8;
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- u32 txcnt:8;
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- u32 pad2:7;
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- u32 clr:1;
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-} msdc_fifocs_reg;
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-typedef struct {
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- u32 val;
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-} msdc_txdat_reg;
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-typedef struct {
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- u32 val;
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-} msdc_rxdat_reg;
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-typedef struct {
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- u32 sdiowkup:1;
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- u32 inswkup:1;
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- u32 pad1:14;
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- u32 buswidth:2;
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- u32 pad2:1;
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- u32 sdio:1;
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- u32 sdioide:1;
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- u32 intblkgap:1;
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- u32 pad4:2;
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- u32 dtoc:8;
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-} sdc_cfg_reg;
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-typedef struct {
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- u32 cmd:6;
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- u32 brk:1;
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- u32 rsptyp:3;
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- u32 pad1:1;
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- u32 dtype:2;
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- u32 rw:1;
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- u32 stop:1;
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- u32 goirq:1;
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- u32 blklen:12;
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- u32 atocmd:2;
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- u32 volswth:1;
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- u32 pad2:1;
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-} sdc_cmd_reg;
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-typedef struct {
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- u32 arg;
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-} sdc_arg_reg;
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-typedef struct {
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- u32 sdcbusy:1;
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- u32 cmdbusy:1;
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- u32 pad:29;
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- u32 swrcmpl:1;
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-} sdc_sts_reg;
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-typedef struct {
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- u32 val;
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-} sdc_resp0_reg;
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-typedef struct {
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- u32 val;
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-} sdc_resp1_reg;
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-typedef struct {
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- u32 val;
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-} sdc_resp2_reg;
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-typedef struct {
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- u32 val;
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-} sdc_resp3_reg;
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-typedef struct {
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- u32 num;
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-} sdc_blknum_reg;
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-typedef struct {
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- u32 sts;
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-} sdc_csts_reg;
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-typedef struct {
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- u32 sts;
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-} sdc_cstsen_reg;
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-typedef struct {
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- u32 datcrcsts:8;
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- u32 ddrcrcsts:4;
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- u32 pad:20;
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-} sdc_datcrcsts_reg;
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-typedef struct {
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- u32 bootstart:1;
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- u32 bootstop:1;
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- u32 bootmode:1;
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- u32 pad1:9;
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- u32 bootwaidly:3;
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- u32 bootsupp:1;
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- u32 pad2:16;
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-} emmc_cfg0_reg;
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-typedef struct {
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- u32 bootcrctmc:16;
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- u32 pad:4;
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- u32 bootacktmc:12;
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-} emmc_cfg1_reg;
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-typedef struct {
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- u32 bootcrcerr:1;
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- u32 bootackerr:1;
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- u32 bootdattmo:1;
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- u32 bootacktmo:1;
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- u32 bootupstate:1;
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- u32 bootackrcv:1;
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- u32 bootdatrcv:1;
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- u32 pad:25;
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-} emmc_sts_reg;
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-typedef struct {
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- u32 bootrst:1;
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- u32 pad:31;
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-} emmc_iocon_reg;
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-typedef struct {
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- u32 val;
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-} msdc_acmd_resp_reg;
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-typedef struct {
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- u32 tunesel:4;
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- u32 pad:28;
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-} msdc_acmd19_trg_reg;
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-typedef struct {
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- u32 val;
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-} msdc_acmd19_sts_reg;
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-typedef struct {
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- u32 addr;
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-} msdc_dma_sa_reg;
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-typedef struct {
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- u32 addr;
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-} msdc_dma_ca_reg;
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-typedef struct {
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- u32 start:1;
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- u32 stop:1;
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- u32 resume:1;
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- u32 pad1:5;
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- u32 mode:1;
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- u32 pad2:1;
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- u32 lastbuf:1;
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- u32 pad3:1;
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- u32 brustsz:3;
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- u32 pad4:1;
|
|
|
- u32 xfersz:16;
|
|
|
-} msdc_dma_ctrl_reg;
|
|
|
-typedef struct {
|
|
|
- u32 status:1;
|
|
|
- u32 decsen:1;
|
|
|
- u32 pad1:2;
|
|
|
- u32 bdcsen:1;
|
|
|
- u32 gpdcsen:1;
|
|
|
- u32 pad2:26;
|
|
|
-} msdc_dma_cfg_reg;
|
|
|
-typedef struct {
|
|
|
- u32 sel:16;
|
|
|
- u32 pad2:16;
|
|
|
-} msdc_dbg_sel_reg;
|
|
|
-typedef struct {
|
|
|
- u32 val;
|
|
|
-} msdc_dbg_out_reg;
|
|
|
-typedef struct {
|
|
|
- u32 clkdrvn:3;
|
|
|
- u32 rsv0:1;
|
|
|
- u32 clkdrvp:3;
|
|
|
- u32 rsv1:1;
|
|
|
- u32 clksr:1;
|
|
|
- u32 rsv2:7;
|
|
|
- u32 clkpd:1;
|
|
|
- u32 clkpu:1;
|
|
|
- u32 clksmt:1;
|
|
|
- u32 clkies:1;
|
|
|
- u32 clktdsel:4;
|
|
|
- u32 clkrdsel:8;
|
|
|
-} msdc_pad_ctl0_reg;
|
|
|
-typedef struct {
|
|
|
- u32 cmddrvn:3;
|
|
|
- u32 rsv0:1;
|
|
|
- u32 cmddrvp:3;
|
|
|
- u32 rsv1:1;
|
|
|
- u32 cmdsr:1;
|
|
|
- u32 rsv2:7;
|
|
|
- u32 cmdpd:1;
|
|
|
- u32 cmdpu:1;
|
|
|
- u32 cmdsmt:1;
|
|
|
- u32 cmdies:1;
|
|
|
- u32 cmdtdsel:4;
|
|
|
- u32 cmdrdsel:8;
|
|
|
-} msdc_pad_ctl1_reg;
|
|
|
-typedef struct {
|
|
|
- u32 datdrvn:3;
|
|
|
- u32 rsv0:1;
|
|
|
- u32 datdrvp:3;
|
|
|
- u32 rsv1:1;
|
|
|
- u32 datsr:1;
|
|
|
- u32 rsv2:7;
|
|
|
- u32 datpd:1;
|
|
|
- u32 datpu:1;
|
|
|
- u32 datsmt:1;
|
|
|
- u32 daties:1;
|
|
|
- u32 dattdsel:4;
|
|
|
- u32 datrdsel:8;
|
|
|
-} msdc_pad_ctl2_reg;
|
|
|
-typedef struct {
|
|
|
- u32 wrrxdly:3;
|
|
|
- u32 pad1:5;
|
|
|
- u32 rdrxdly:8;
|
|
|
- u32 pad2:16;
|
|
|
-} msdc_pad_tune_reg;
|
|
|
-typedef struct {
|
|
|
- u32 dat0:5;
|
|
|
- u32 rsv0:3;
|
|
|
- u32 dat1:5;
|
|
|
- u32 rsv1:3;
|
|
|
- u32 dat2:5;
|
|
|
- u32 rsv2:3;
|
|
|
- u32 dat3:5;
|
|
|
- u32 rsv3:3;
|
|
|
-} msdc_dat_rddly0;
|
|
|
-typedef struct {
|
|
|
- u32 dat4:5;
|
|
|
- u32 rsv4:3;
|
|
|
- u32 dat5:5;
|
|
|
- u32 rsv5:3;
|
|
|
- u32 dat6:5;
|
|
|
- u32 rsv6:3;
|
|
|
- u32 dat7:5;
|
|
|
- u32 rsv7:3;
|
|
|
-} msdc_dat_rddly1;
|
|
|
-typedef struct {
|
|
|
- u32 dbg0sel:8;
|
|
|
- u32 dbg1sel:6;
|
|
|
- u32 pad1:2;
|
|
|
- u32 dbg2sel:6;
|
|
|
- u32 pad2:2;
|
|
|
- u32 dbg3sel:6;
|
|
|
- u32 pad3:2;
|
|
|
-} msdc_hw_dbg_reg;
|
|
|
-typedef struct {
|
|
|
- u32 val;
|
|
|
-} msdc_version_reg;
|
|
|
-typedef struct {
|
|
|
- u32 val;
|
|
|
-} msdc_eco_ver_reg;
|
|
|
+struct msdc_cfg_reg {
|
|
|
+ u32 msdc:1;
|
|
|
+ u32 ckpwn:1;
|
|
|
+ u32 rst:1;
|
|
|
+ u32 pio:1;
|
|
|
+ u32 ckdrven:1;
|
|
|
+ u32 start18v:1;
|
|
|
+ u32 pass18v:1;
|
|
|
+ u32 ckstb:1;
|
|
|
+ u32 ckdiv:8;
|
|
|
+ u32 ckmod:2;
|
|
|
+ u32 pad:14;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_iocon_reg {
|
|
|
+ u32 sdr104cksel:1;
|
|
|
+ u32 rsmpl:1;
|
|
|
+ u32 dsmpl:1;
|
|
|
+ u32 ddlysel:1;
|
|
|
+ u32 ddr50ckd:1;
|
|
|
+ u32 dsplsel:1;
|
|
|
+ u32 pad1:10;
|
|
|
+ u32 d0spl:1;
|
|
|
+ u32 d1spl:1;
|
|
|
+ u32 d2spl:1;
|
|
|
+ u32 d3spl:1;
|
|
|
+ u32 d4spl:1;
|
|
|
+ u32 d5spl:1;
|
|
|
+ u32 d6spl:1;
|
|
|
+ u32 d7spl:1;
|
|
|
+ u32 riscsz:1;
|
|
|
+ u32 pad2:7;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_ps_reg {
|
|
|
+ u32 cden:1;
|
|
|
+ u32 cdsts:1;
|
|
|
+ u32 pad1:10;
|
|
|
+ u32 cddebounce:4;
|
|
|
+ u32 dat:8;
|
|
|
+ u32 cmd:1;
|
|
|
+ u32 pad2:6;
|
|
|
+ u32 wp:1;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_int_reg {
|
|
|
+ u32 mmcirq:1;
|
|
|
+ u32 cdsc:1;
|
|
|
+ u32 pad1:1;
|
|
|
+ u32 atocmdrdy:1;
|
|
|
+ u32 atocmdtmo:1;
|
|
|
+ u32 atocmdcrc:1;
|
|
|
+ u32 dmaqempty:1;
|
|
|
+ u32 sdioirq:1;
|
|
|
+ u32 cmdrdy:1;
|
|
|
+ u32 cmdtmo:1;
|
|
|
+ u32 rspcrc:1;
|
|
|
+ u32 csta:1;
|
|
|
+ u32 xfercomp:1;
|
|
|
+ u32 dxferdone:1;
|
|
|
+ u32 dattmo:1;
|
|
|
+ u32 datcrc:1;
|
|
|
+ u32 atocmd19done:1;
|
|
|
+ u32 pad2:15;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_inten_reg {
|
|
|
+ u32 mmcirq:1;
|
|
|
+ u32 cdsc:1;
|
|
|
+ u32 pad1:1;
|
|
|
+ u32 atocmdrdy:1;
|
|
|
+ u32 atocmdtmo:1;
|
|
|
+ u32 atocmdcrc:1;
|
|
|
+ u32 dmaqempty:1;
|
|
|
+ u32 sdioirq:1;
|
|
|
+ u32 cmdrdy:1;
|
|
|
+ u32 cmdtmo:1;
|
|
|
+ u32 rspcrc:1;
|
|
|
+ u32 csta:1;
|
|
|
+ u32 xfercomp:1;
|
|
|
+ u32 dxferdone:1;
|
|
|
+ u32 dattmo:1;
|
|
|
+ u32 datcrc:1;
|
|
|
+ u32 atocmd19done:1;
|
|
|
+ u32 pad2:15;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_fifocs_reg {
|
|
|
+ u32 rxcnt:8;
|
|
|
+ u32 pad1:8;
|
|
|
+ u32 txcnt:8;
|
|
|
+ u32 pad2:7;
|
|
|
+ u32 clr:1;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_txdat_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_rxdat_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_cfg_reg {
|
|
|
+ u32 sdiowkup:1;
|
|
|
+ u32 inswkup:1;
|
|
|
+ u32 pad1:14;
|
|
|
+ u32 buswidth:2;
|
|
|
+ u32 pad2:1;
|
|
|
+ u32 sdio:1;
|
|
|
+ u32 sdioide:1;
|
|
|
+ u32 intblkgap:1;
|
|
|
+ u32 pad4:2;
|
|
|
+ u32 dtoc:8;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_cmd_reg {
|
|
|
+ u32 cmd:6;
|
|
|
+ u32 brk:1;
|
|
|
+ u32 rsptyp:3;
|
|
|
+ u32 pad1:1;
|
|
|
+ u32 dtype:2;
|
|
|
+ u32 rw:1;
|
|
|
+ u32 stop:1;
|
|
|
+ u32 goirq:1;
|
|
|
+ u32 blklen:12;
|
|
|
+ u32 atocmd:2;
|
|
|
+ u32 volswth:1;
|
|
|
+ u32 pad2:1;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_arg_reg {
|
|
|
+ u32 arg;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_sts_reg {
|
|
|
+ u32 sdcbusy:1;
|
|
|
+ u32 cmdbusy:1;
|
|
|
+ u32 pad:29;
|
|
|
+ u32 swrcmpl:1;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_resp0_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_resp1_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_resp2_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_resp3_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_blknum_reg {
|
|
|
+ u32 num;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_csts_reg {
|
|
|
+ u32 sts;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_cstsen_reg {
|
|
|
+ u32 sts;
|
|
|
+};
|
|
|
+
|
|
|
+struct sdc_datcrcsts_reg {
|
|
|
+ u32 datcrcsts:8;
|
|
|
+ u32 ddrcrcsts:4;
|
|
|
+ u32 pad:20;
|
|
|
+};
|
|
|
+
|
|
|
+struct emmc_cfg0_reg {
|
|
|
+ u32 bootstart:1;
|
|
|
+ u32 bootstop:1;
|
|
|
+ u32 bootmode:1;
|
|
|
+ u32 pad1:9;
|
|
|
+ u32 bootwaidly:3;
|
|
|
+ u32 bootsupp:1;
|
|
|
+ u32 pad2:16;
|
|
|
+};
|
|
|
+
|
|
|
+struct emmc_cfg1_reg {
|
|
|
+ u32 bootcrctmc:16;
|
|
|
+ u32 pad:4;
|
|
|
+ u32 bootacktmc:12;
|
|
|
+};
|
|
|
+
|
|
|
+struct emmc_sts_reg {
|
|
|
+ u32 bootcrcerr:1;
|
|
|
+ u32 bootackerr:1;
|
|
|
+ u32 bootdattmo:1;
|
|
|
+ u32 bootacktmo:1;
|
|
|
+ u32 bootupstate:1;
|
|
|
+ u32 bootackrcv:1;
|
|
|
+ u32 bootdatrcv:1;
|
|
|
+ u32 pad:25;
|
|
|
+};
|
|
|
+
|
|
|
+struct emmc_iocon_reg {
|
|
|
+ u32 bootrst:1;
|
|
|
+ u32 pad:31;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_acmd_resp_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_acmd19_trg_reg {
|
|
|
+ u32 tunesel:4;
|
|
|
+ u32 pad:28;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_acmd19_sts_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dma_sa_reg {
|
|
|
+ u32 addr;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dma_ca_reg {
|
|
|
+ u32 addr;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dma_ctrl_reg {
|
|
|
+ u32 start:1;
|
|
|
+ u32 stop:1;
|
|
|
+ u32 resume:1;
|
|
|
+ u32 pad1:5;
|
|
|
+ u32 mode:1;
|
|
|
+ u32 pad2:1;
|
|
|
+ u32 lastbuf:1;
|
|
|
+ u32 pad3:1;
|
|
|
+ u32 brustsz:3;
|
|
|
+ u32 pad4:1;
|
|
|
+ u32 xfersz:16;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dma_cfg_reg {
|
|
|
+ u32 status:1;
|
|
|
+ u32 decsen:1;
|
|
|
+ u32 pad1:2;
|
|
|
+ u32 bdcsen:1;
|
|
|
+ u32 gpdcsen:1;
|
|
|
+ u32 pad2:26;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dbg_sel_reg {
|
|
|
+ u32 sel:16;
|
|
|
+ u32 pad2:16;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dbg_out_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_pad_ctl0_reg {
|
|
|
+ u32 clkdrvn:3;
|
|
|
+ u32 rsv0:1;
|
|
|
+ u32 clkdrvp:3;
|
|
|
+ u32 rsv1:1;
|
|
|
+ u32 clksr:1;
|
|
|
+ u32 rsv2:7;
|
|
|
+ u32 clkpd:1;
|
|
|
+ u32 clkpu:1;
|
|
|
+ u32 clksmt:1;
|
|
|
+ u32 clkies:1;
|
|
|
+ u32 clktdsel:4;
|
|
|
+ u32 clkrdsel:8;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_pad_ctl1_reg {
|
|
|
+ u32 cmddrvn:3;
|
|
|
+ u32 rsv0:1;
|
|
|
+ u32 cmddrvp:3;
|
|
|
+ u32 rsv1:1;
|
|
|
+ u32 cmdsr:1;
|
|
|
+ u32 rsv2:7;
|
|
|
+ u32 cmdpd:1;
|
|
|
+ u32 cmdpu:1;
|
|
|
+ u32 cmdsmt:1;
|
|
|
+ u32 cmdies:1;
|
|
|
+ u32 cmdtdsel:4;
|
|
|
+ u32 cmdrdsel:8;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_pad_ctl2_reg {
|
|
|
+ u32 datdrvn:3;
|
|
|
+ u32 rsv0:1;
|
|
|
+ u32 datdrvp:3;
|
|
|
+ u32 rsv1:1;
|
|
|
+ u32 datsr:1;
|
|
|
+ u32 rsv2:7;
|
|
|
+ u32 datpd:1;
|
|
|
+ u32 datpu:1;
|
|
|
+ u32 datsmt:1;
|
|
|
+ u32 daties:1;
|
|
|
+ u32 dattdsel:4;
|
|
|
+ u32 datrdsel:8;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_pad_tune_reg {
|
|
|
+ u32 wrrxdly:3;
|
|
|
+ u32 pad1:5;
|
|
|
+ u32 rdrxdly:8;
|
|
|
+ u32 pad2:16;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dat_rddly0 {
|
|
|
+ u32 dat0:5;
|
|
|
+ u32 rsv0:3;
|
|
|
+ u32 dat1:5;
|
|
|
+ u32 rsv1:3;
|
|
|
+ u32 dat2:5;
|
|
|
+ u32 rsv2:3;
|
|
|
+ u32 dat3:5;
|
|
|
+ u32 rsv3:3;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_dat_rddly1 {
|
|
|
+ u32 dat4:5;
|
|
|
+ u32 rsv4:3;
|
|
|
+ u32 dat5:5;
|
|
|
+ u32 rsv5:3;
|
|
|
+ u32 dat6:5;
|
|
|
+ u32 rsv6:3;
|
|
|
+ u32 dat7:5;
|
|
|
+ u32 rsv7:3;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_hw_dbg_reg {
|
|
|
+ u32 dbg0sel:8;
|
|
|
+ u32 dbg1sel:6;
|
|
|
+ u32 pad1:2;
|
|
|
+ u32 dbg2sel:6;
|
|
|
+ u32 pad2:2;
|
|
|
+ u32 dbg3sel:6;
|
|
|
+ u32 pad3:2;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_version_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
+
|
|
|
+struct msdc_eco_ver_reg {
|
|
|
+ u32 val;
|
|
|
+};
|
|
|
|
|
|
struct msdc_regs {
|
|
|
- msdc_cfg_reg msdc_cfg; /* base+0x00h */
|
|
|
- msdc_iocon_reg msdc_iocon; /* base+0x04h */
|
|
|
- msdc_ps_reg msdc_ps; /* base+0x08h */
|
|
|
- msdc_int_reg msdc_int; /* base+0x0ch */
|
|
|
- msdc_inten_reg msdc_inten; /* base+0x10h */
|
|
|
- msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
|
|
|
- msdc_txdat_reg msdc_txdat; /* base+0x18h */
|
|
|
- msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
|
|
|
- u32 rsv1[4];
|
|
|
- sdc_cfg_reg sdc_cfg; /* base+0x30h */
|
|
|
- sdc_cmd_reg sdc_cmd; /* base+0x34h */
|
|
|
- sdc_arg_reg sdc_arg; /* base+0x38h */
|
|
|
- sdc_sts_reg sdc_sts; /* base+0x3ch */
|
|
|
- sdc_resp0_reg sdc_resp0; /* base+0x40h */
|
|
|
- sdc_resp1_reg sdc_resp1; /* base+0x44h */
|
|
|
- sdc_resp2_reg sdc_resp2; /* base+0x48h */
|
|
|
- sdc_resp3_reg sdc_resp3; /* base+0x4ch */
|
|
|
- sdc_blknum_reg sdc_blknum; /* base+0x50h */
|
|
|
- u32 rsv2[1];
|
|
|
- sdc_csts_reg sdc_csts; /* base+0x58h */
|
|
|
- sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
|
|
|
- sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
|
|
|
- u32 rsv3[3];
|
|
|
- emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
|
|
|
- emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
|
|
|
- emmc_sts_reg emmc_sts; /* base+0x78h */
|
|
|
- emmc_iocon_reg emmc_iocon; /* base+0x7ch */
|
|
|
- msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
|
|
|
- msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
|
|
|
- msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
|
|
|
- u32 rsv4[1];
|
|
|
- msdc_dma_sa_reg dma_sa; /* base+0x90h */
|
|
|
- msdc_dma_ca_reg dma_ca; /* base+0x94h */
|
|
|
- msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
|
|
|
- msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
|
|
|
- msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
|
|
|
- msdc_dbg_out_reg dbg_out; /* base+0xa4h */
|
|
|
- u32 rsv5[2];
|
|
|
- u32 patch0; /* base+0xb0h */
|
|
|
- u32 patch1; /* base+0xb4h */
|
|
|
- u32 rsv6[10];
|
|
|
- msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
|
|
|
- msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
|
|
|
- msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
|
|
|
- msdc_pad_tune_reg pad_tune; /* base+0xech */
|
|
|
- msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
|
|
|
- msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
|
|
|
- msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
|
|
|
- u32 rsv7[1];
|
|
|
- msdc_version_reg version; /* base+0x100h */
|
|
|
- msdc_eco_ver_reg eco_ver; /* base+0x104h */
|
|
|
-};
|
|
|
-
|
|
|
-struct scatterlist_ex {
|
|
|
- u32 cmd;
|
|
|
- u32 arg;
|
|
|
- u32 sglen;
|
|
|
- struct scatterlist *sg;
|
|
|
-};
|
|
|
-
|
|
|
-#define DMA_FLAG_NONE (0x00000000)
|
|
|
-#define DMA_FLAG_EN_CHKSUM (0x00000001)
|
|
|
-#define DMA_FLAG_PAD_BLOCK (0x00000002)
|
|
|
-#define DMA_FLAG_PAD_DWORD (0x00000004)
|
|
|
+ struct msdc_cfg_reg msdc_cfg; /* base+0x00h */
|
|
|
+ struct msdc_iocon_reg msdc_iocon; /* base+0x04h */
|
|
|
+ struct msdc_ps_reg msdc_ps; /* base+0x08h */
|
|
|
+ struct msdc_int_reg msdc_int; /* base+0x0ch */
|
|
|
+ struct msdc_inten_reg msdc_inten; /* base+0x10h */
|
|
|
+ struct msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
|
|
|
+ struct msdc_txdat_reg msdc_txdat; /* base+0x18h */
|
|
|
+ struct msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
|
|
|
+ u32 rsv1[4];
|
|
|
+ struct sdc_cfg_reg sdc_cfg; /* base+0x30h */
|
|
|
+ struct sdc_cmd_reg sdc_cmd; /* base+0x34h */
|
|
|
+ struct sdc_arg_reg sdc_arg; /* base+0x38h */
|
|
|
+ struct sdc_sts_reg sdc_sts; /* base+0x3ch */
|
|
|
+ struct sdc_resp0_reg sdc_resp0; /* base+0x40h */
|
|
|
+ struct sdc_resp1_reg sdc_resp1; /* base+0x44h */
|
|
|
+ struct sdc_resp2_reg sdc_resp2; /* base+0x48h */
|
|
|
+ struct sdc_resp3_reg sdc_resp3; /* base+0x4ch */
|
|
|
+ struct sdc_blknum_reg sdc_blknum; /* base+0x50h */
|
|
|
+ u32 rsv2[1];
|
|
|
+ struct sdc_csts_reg sdc_csts; /* base+0x58h */
|
|
|
+ struct sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
|
|
|
+ struct sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
|
|
|
+ u32 rsv3[3];
|
|
|
+ struct emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
|
|
|
+ struct emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
|
|
|
+ struct emmc_sts_reg emmc_sts; /* base+0x78h */
|
|
|
+ struct emmc_iocon_reg emmc_iocon; /* base+0x7ch */
|
|
|
+ struct msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
|
|
|
+ struct msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
|
|
|
+ struct msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
|
|
|
+ u32 rsv4[1];
|
|
|
+ struct msdc_dma_sa_reg dma_sa; /* base+0x90h */
|
|
|
+ struct msdc_dma_ca_reg dma_ca; /* base+0x94h */
|
|
|
+ struct msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
|
|
|
+ struct msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
|
|
|
+ struct msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
|
|
|
+ struct msdc_dbg_out_reg dbg_out; /* base+0xa4h */
|
|
|
+ u32 rsv5[2];
|
|
|
+ u32 patch0; /* base+0xb0h */
|
|
|
+ u32 patch1; /* base+0xb4h */
|
|
|
+ u32 rsv6[10];
|
|
|
+ struct msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
|
|
|
+ struct msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
|
|
|
+ struct msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
|
|
|
+ struct msdc_pad_tune_reg pad_tune; /* base+0xech */
|
|
|
+ struct msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
|
|
|
+ struct msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
|
|
|
+ struct msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
|
|
|
+ u32 rsv7[1];
|
|
|
+ struct msdc_version_reg version; /* base+0x100h */
|
|
|
+ struct msdc_eco_ver_reg eco_ver; /* base+0x104h */
|
|
|
+};
|
|
|
|
|
|
struct msdc_dma {
|
|
|
- u32 flags; /* flags */
|
|
|
- u32 xfersz; /* xfer size in bytes */
|
|
|
- u32 sglen; /* size of scatter list */
|
|
|
- u32 blklen; /* block size */
|
|
|
- struct scatterlist *sg; /* I/O scatter list */
|
|
|
- struct scatterlist_ex *esg; /* extended I/O scatter list */
|
|
|
- u8 mode; /* dma mode */
|
|
|
- u8 burstsz; /* burst size */
|
|
|
- u8 intr; /* dma done interrupt */
|
|
|
- u8 padding; /* padding */
|
|
|
- u32 cmd; /* enhanced mode command */
|
|
|
- u32 arg; /* enhanced mode arg */
|
|
|
- u32 rsp; /* enhanced mode command response */
|
|
|
- u32 autorsp; /* auto command response */
|
|
|
-
|
|
|
- gpd_t *gpd; /* pointer to gpd array */
|
|
|
- bd_t *bd; /* pointer to bd array */
|
|
|
- dma_addr_t gpd_addr; /* the physical address of gpd array */
|
|
|
- dma_addr_t bd_addr; /* the physical address of bd array */
|
|
|
- u32 used_gpd; /* the number of used gpd elements */
|
|
|
- u32 used_bd; /* the number of used bd elements */
|
|
|
-};
|
|
|
-
|
|
|
-struct msdc_host
|
|
|
-{
|
|
|
- struct msdc_hw *hw;
|
|
|
+ u32 sglen; /* size of scatter list */
|
|
|
+ struct scatterlist *sg; /* I/O scatter list */
|
|
|
+ u8 mode; /* dma mode */
|
|
|
+
|
|
|
+ struct gpd *gpd; /* pointer to gpd array */
|
|
|
+ struct bd *bd; /* pointer to bd array */
|
|
|
+ dma_addr_t gpd_addr; /* the physical address of gpd array */
|
|
|
+ dma_addr_t bd_addr; /* the physical address of bd array */
|
|
|
+};
|
|
|
|
|
|
- struct mmc_host *mmc; /* mmc structure */
|
|
|
- struct mmc_command *cmd;
|
|
|
- struct mmc_data *data;
|
|
|
- struct mmc_request *mrq;
|
|
|
- int cmd_rsp;
|
|
|
- int cmd_rsp_done;
|
|
|
- int cmd_r1b_done;
|
|
|
+struct msdc_host {
|
|
|
+ struct msdc_hw *hw;
|
|
|
|
|
|
- int error;
|
|
|
- spinlock_t lock; /* mutex */
|
|
|
- struct semaphore sem;
|
|
|
+ struct mmc_host *mmc; /* mmc structure */
|
|
|
+ struct mmc_command *cmd;
|
|
|
+ struct mmc_data *data;
|
|
|
+ struct mmc_request *mrq;
|
|
|
+ int cmd_rsp;
|
|
|
|
|
|
- u32 blksz; /* host block size */
|
|
|
- u32 base; /* host base address */
|
|
|
- int id; /* host id */
|
|
|
- int pwr_ref; /* core power reference count */
|
|
|
+ int error;
|
|
|
+ spinlock_t lock; /* mutex */
|
|
|
+ struct semaphore sem;
|
|
|
|
|
|
- u32 xfer_size; /* total transferred size */
|
|
|
+ u32 blksz; /* host block size */
|
|
|
+ void __iomem *base; /* host base address */
|
|
|
+ int id; /* host id */
|
|
|
+ int pwr_ref; /* core power reference count */
|
|
|
|
|
|
- struct msdc_dma dma; /* dma channel */
|
|
|
- u32 dma_addr; /* dma transfer address */
|
|
|
- u32 dma_left_size; /* dma transfer left size */
|
|
|
- u32 dma_xfer_size; /* dma transfer size in bytes */
|
|
|
- int dma_xfer; /* dma transfer mode */
|
|
|
+ u32 xfer_size; /* total transferred size */
|
|
|
|
|
|
- u32 timeout_ns; /* data timeout ns */
|
|
|
- u32 timeout_clks; /* data timeout clks */
|
|
|
+ struct msdc_dma dma; /* dma channel */
|
|
|
+ u32 dma_xfer_size; /* dma transfer size in bytes */
|
|
|
|
|
|
- atomic_t abort; /* abort transfer */
|
|
|
+ u32 timeout_ns; /* data timeout ns */
|
|
|
+ u32 timeout_clks; /* data timeout clks */
|
|
|
|
|
|
- int irq; /* host interrupt */
|
|
|
+ int irq; /* host interrupt */
|
|
|
|
|
|
- struct tasklet_struct card_tasklet;
|
|
|
-#if 0
|
|
|
- struct work_struct card_workqueue;
|
|
|
-#else
|
|
|
- struct delayed_work card_delaywork;
|
|
|
-#endif
|
|
|
+ struct delayed_work card_delaywork;
|
|
|
+
|
|
|
+ struct completion cmd_done;
|
|
|
+ struct completion xfer_done;
|
|
|
+ struct pm_message pm_state;
|
|
|
+
|
|
|
+ u32 mclk; /* mmc subsystem clock */
|
|
|
+ u32 hclk; /* host clock speed */
|
|
|
+ u32 sclk; /* SD/MS clock speed */
|
|
|
+ u8 core_clkon; /* Host core clock on ? */
|
|
|
+ u8 card_clkon; /* Card clock on ? */
|
|
|
+ u8 core_power; /* core power */
|
|
|
+ u8 power_mode; /* host power mode */
|
|
|
+ u8 card_inserted; /* card inserted ? */
|
|
|
+ u8 suspend; /* host suspended ? */
|
|
|
+ u8 app_cmd; /* for app command */
|
|
|
+ u32 app_cmd_arg;
|
|
|
+};
|
|
|
+
|
|
|
+#define sdr_read8(reg) readb(reg)
|
|
|
+#define sdr_read32(reg) readl(reg)
|
|
|
+#define sdr_write8(reg, val) writeb(val, reg)
|
|
|
+#define sdr_write32(reg, val) writel(val, reg)
|
|
|
|
|
|
- struct completion cmd_done;
|
|
|
- struct completion xfer_done;
|
|
|
- struct pm_message pm_state;
|
|
|
-
|
|
|
- u32 mclk; /* mmc subsystem clock */
|
|
|
- u32 hclk; /* host clock speed */
|
|
|
- u32 sclk; /* SD/MS clock speed */
|
|
|
- u8 core_clkon; /* Host core clock on ? */
|
|
|
- u8 card_clkon; /* Card clock on ? */
|
|
|
- u8 core_power; /* core power */
|
|
|
- u8 power_mode; /* host power mode */
|
|
|
- u8 card_inserted; /* card inserted ? */
|
|
|
- u8 suspend; /* host suspended ? */
|
|
|
- u8 reserved;
|
|
|
- u8 app_cmd; /* for app command */
|
|
|
- u32 app_cmd_arg;
|
|
|
- u64 starttime;
|
|
|
-};
|
|
|
-
|
|
|
-static inline unsigned int uffs(unsigned int x)
|
|
|
+static inline void sdr_set_bits(void __iomem *reg, u32 bs)
|
|
|
{
|
|
|
- unsigned int r = 1;
|
|
|
-
|
|
|
- if (!x)
|
|
|
- return 0;
|
|
|
- if (!(x & 0xffff)) {
|
|
|
- x >>= 16;
|
|
|
- r += 16;
|
|
|
- }
|
|
|
- if (!(x & 0xff)) {
|
|
|
- x >>= 8;
|
|
|
- r += 8;
|
|
|
- }
|
|
|
- if (!(x & 0xf)) {
|
|
|
- x >>= 4;
|
|
|
- r += 4;
|
|
|
- }
|
|
|
- if (!(x & 3)) {
|
|
|
- x >>= 2;
|
|
|
- r += 2;
|
|
|
- }
|
|
|
- if (!(x & 1)) {
|
|
|
- x >>= 1;
|
|
|
- r += 1;
|
|
|
- }
|
|
|
- return r;
|
|
|
+ u32 val = readl(reg);
|
|
|
+
|
|
|
+ val |= bs;
|
|
|
+ writel(val, reg);
|
|
|
}
|
|
|
-#define sdr_read8(reg) __raw_readb(reg)
|
|
|
-#define sdr_read16(reg) __raw_readw(reg)
|
|
|
-#define sdr_read32(reg) __raw_readl(reg)
|
|
|
-#define sdr_write8(reg,val) __raw_writeb(val,reg)
|
|
|
-#define sdr_write16(reg,val) __raw_writew(val,reg)
|
|
|
-#define sdr_write32(reg,val) __raw_writel(val,reg)
|
|
|
-
|
|
|
-#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
|
|
|
-#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
|
|
|
-
|
|
|
-#define sdr_set_field(reg,field,val) \
|
|
|
- do { \
|
|
|
- volatile unsigned int tv = sdr_read32(reg); \
|
|
|
- tv &= ~(field); \
|
|
|
- tv |= ((val) << (uffs((unsigned int)field) - 1)); \
|
|
|
- sdr_write32(reg,tv); \
|
|
|
- } while(0)
|
|
|
-#define sdr_get_field(reg,field,val) \
|
|
|
- do { \
|
|
|
- volatile unsigned int tv = sdr_read32(reg); \
|
|
|
- val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
|
|
|
- } while(0)
|
|
|
|
|
|
-#endif
|
|
|
+static inline void sdr_clr_bits(void __iomem *reg, u32 bs)
|
|
|
+{
|
|
|
+ u32 val = readl(reg);
|
|
|
+
|
|
|
+ val &= ~bs;
|
|
|
+ writel(val, reg);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)
|
|
|
+{
|
|
|
+ unsigned int tv = readl(reg);
|
|
|
|
|
|
+ tv &= ~field;
|
|
|
+ tv |= ((val) << (ffs((unsigned int)field) - 1));
|
|
|
+ writel(tv, reg);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
|
|
|
+{
|
|
|
+ unsigned int tv = readl(reg);
|
|
|
+ *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
|
|
|
+}
|
|
|
+
|
|
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+#endif
|
Rosen Penev