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@@ -166,6 +166,8 @@
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reg-io-width = <4>;
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no-loopback-test;
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+ clock-frequency = <40000000>;
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+
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resets = <&rstctrl 12>;
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reset-names = "uartl";
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@@ -184,6 +186,8 @@
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reg-io-width = <4>;
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no-loopback-test;
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+ clock-frequency = <40000000>;
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+
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resets = <&rstctrl 19>;
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reset-names = "uart1";
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@@ -204,6 +208,8 @@
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reg-io-width = <4>;
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no-loopback-test;
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+ clock-frequency = <40000000>;
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+
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resets = <&rstctrl 20>;
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reset-names = "uart2";
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@@ -344,6 +350,11 @@
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#reset-cells = <1>;
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};
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+ clkctrl: clkctrl {
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+ compatible = "ralink,rt2880-clock";
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+ #clock-cells = <1>;
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+ };
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+
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usbphy: usbphy@10120000 {
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compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy";
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reg = <0x10120000 0x4000>;
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@@ -351,6 +362,8 @@
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resets = <&rstctrl 22 &rstctrl 25>;
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reset-names = "host", "device";
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+ clocks = <&clkctrl 22 &clkctrl 25>;
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+ clock-names = "host", "device";
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};
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sdhci: sdhci@10130000 {
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@@ -420,12 +433,14 @@
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#address-cells = <3>;
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#size-cells = <2>;
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- resets = <&rstctrl 26>;
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- reset-names = "pcie0";
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-
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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+ resets = <&rstctrl 26 &rstctrl 27>;
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+ reset-names = "pcie0", "pcie1";
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+ clocks = <&clkctrl 26 &clkctrl 27>;
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+ clock-names = "pcie0", "pcie1";
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+
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status = "disabled";
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device_type = "pci";
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