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0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch

0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch 3.6 KB
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  1. From e0e3768b73daae674c69db1f71718894274b7bfc Mon Sep 17 00:00:00 2001
    2. 

  2. From: Ryder Lee <[email protected]>
    3. 

  3. Date: Thu, 4 Jan 2018 15:44:07 +0800
    4. 

  4. Subject: [PATCH 184/224] ASoC: mediatek: add some core clocks for MT2701 AFE
    5. 

  5. 

  6. Add three core clocks for MT2701 AFE.
    7. 

  7. 

  8. Signed-off-by: Ryder Lee <[email protected]>
    9. 

  9. Signed-off-by: Mark Brown <[email protected]>
    10. 

  10. ---
    11. 

  11.  sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 30 ++++++++++++++++++++++-
    12. 

  12.  sound/soc/mediatek/mt2701/mt2701-afe-common.h     |  3 +++
    13. 

  13.  2 files changed, 32 insertions(+), 1 deletion(-)
    14. 

  14. 

  15. diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
    16. 

  16. index 56a057c78c9a..949fc3a1d025 100644
    17. 

  17. --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
    18. 

  18. +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
    19. 

  19. @@ -18,8 +18,11 @@
    20. 

  20.  #include "mt2701-afe-clock-ctrl.h"
    21. 

  21.  
    22. 

  22.  static const char *const base_clks[] = {
    23. 

  23. +	[MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
    24. 

  24.  	[MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
    25. 

  25.  	[MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
    26. 

  26. +	[MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
    27. 

  27. +	[MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
    28. 

  28.  	[MT2701_AUDSYS_AFE] = "audio_afe_pd",
    29. 

  29.  	[MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
    30. 

  30.  	[MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
    31. 

  31. @@ -169,10 +172,26 @@ static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
    32. 

  32.  	struct mt2701_afe_private *afe_priv = afe->platform_priv;
    33. 

  33.  	int ret;
    34. 

  34.  
    35. 

  35. -	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
    36. 

  36. +	/* Enable infra clock gate */
    37. 

  37. +	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
    38. 

  38.  	if (ret)
    39. 

  39.  		return ret;
    40. 

  40.  
    41. 

  41. +	/* Enable top a1sys clock gate */
    42. 

  42. +	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
    43. 

  43. +	if (ret)
    44. 

  44. +		goto err_a1sys;
    45. 

  45. +
    46. 

  46. +	/* Enable top a2sys clock gate */
    47. 

  47. +	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
    48. 

  48. +	if (ret)
    49. 

  49. +		goto err_a2sys;
    50. 

  50. +
    51. 

  51. +	/* Internal clock gates */
    52. 

  52. +	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
    53. 

  53. +	if (ret)
    54. 

  54. +		goto err_afe;
    55. 

  55. +
    56. 

  56.  	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
    57. 

  57.  	if (ret)
    58. 

  58.  		goto err_audio_a1sys;
    59. 

  59. @@ -193,6 +212,12 @@ static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
    60. 

  60.  	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
    61. 

  61.  err_audio_a1sys:
    62. 

  62.  	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
    63. 

  63. +err_afe:
    64. 

  64. +	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
    65. 

  65. +err_a2sys:
    66. 

  66. +	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
    67. 

  67. +err_a1sys:
    68. 

  68. +	clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
    69. 

  69.  
    70. 

  70.  	return ret;
    71. 

  71.  }
    72. 

  72. @@ -205,6 +230,9 @@ static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
    73. 

  73.  	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
    74. 

  74.  	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
    75. 

  75.  	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
    76. 

  76. +	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
    77. 

  77. +	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
    78. 

  78. +	clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
    79. 

  79.  }
    80. 

  80.  
    81. 

  81.  int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
    82. 

  82. diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-common.h b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
    83. 

  83. index 9a2b301a4c21..ae8ddeacfbfe 100644
    84. 

  84. --- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
    85. 

  85. +++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
    86. 

  86. @@ -61,8 +61,11 @@ enum {
    87. 

  87.  };
    88. 

  88.  
    89. 

  89.  enum audio_base_clock {
    90. 

  90. +	MT2701_INFRA_SYS_AUDIO,
    91. 

  91.  	MT2701_TOP_AUD_MCLK_SRC0,
    92. 

  92.  	MT2701_TOP_AUD_MCLK_SRC1,
    93. 

  93. +	MT2701_TOP_AUD_A1SYS,
    94. 

  94. +	MT2701_TOP_AUD_A2SYS,
    95. 

  95.  	MT2701_AUDSYS_AFE,
    96. 

  96.  	MT2701_AUDSYS_AFE_CONN,
    97. 

  97.  	MT2701_AUDSYS_A1SYS,
    98. 

  98. -- 
    99. 

  99. 2.11.0
    100. 

  100.