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- From 21261e30679118b96ed537d1cdf9e12682fc1b29 Mon Sep 17 00:00:00 2001
- From: Eugen Hristev <[email protected]>
- Date: Wed, 9 Jun 2021 15:00:28 +0200
- Subject: [PATCH 193/247] media: atmel: atmel-sama5d2-isc: fix YUYV format
- SAMA5D2 does not have the YCYC field for the RLP (rounding, limiting,
- packaging) module.
- The YCYC field is supposed to work with interleaved YUV formats like YUYV.
- In SAMA5D2, we have to use YYCC field, which is used for both planar
- formats like YUV420 and interleaved formats like YUYV.
- Fix the according rlp callback to replace the generic YCYC field (which
- makes more sense from a logical point of view) with the required YYCC
- field.
- Fixes: debfa496871c ("media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules")
- Signed-off-by: Eugen Hristev <[email protected]>
- Signed-off-by: Hans Verkuil <[email protected]>
- Signed-off-by: Mauro Carvalho Chehab <[email protected]>
- ---
- .../media/platform/atmel/atmel-sama5d2-isc.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
- --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
- +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
- @@ -255,6 +255,23 @@ static void isc_sama5d2_config_rlp(struc
- struct regmap *regmap = isc->regmap;
- u32 rlp_mode = isc->config.rlp_cfg_mode;
-
- + /*
- + * In sama5d2, the YUV planar modes and the YUYV modes are treated
- + * in the same way in RLP register.
- + * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n)
- + * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n)
- + * but in sama5d2, the YCYC mode does not exist, and YYCC must be
- + * selected for both planar and interleaved modes, as in fact
- + * both modes are supported.
- + *
- + * Thus, if the YCYC mode is selected, replace it with the
- + * sama5d2-compliant mode which is YYCC .
- + */
- + if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) {
- + rlp_mode &= ~ISC_RLP_CFG_MODE_MASK;
- + rlp_mode |= ISC_RLP_CFG_MODE_YYCC;
- + }
- +
- regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
- ISC_RLP_CFG_MODE_MASK, rlp_mode);
- }
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