qcom-ipq8064.dtsi 30 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410
  1. /dts-v1/;
  2. #include "skeleton.dtsi"
  3. #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  4. #include <dt-bindings/mfd/qcom-rpm.h>
  5. #include <dt-bindings/clock/qcom,rpmcc.h>
  6. #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
  7. #include <dt-bindings/soc/qcom,gsbi.h>
  8. #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. #include <dt-bindings/gpio/gpio.h>
  11. / {
  12. model = "Qualcomm IPQ8064";
  13. compatible = "qcom,ipq8064";
  14. interrupt-parent = <&intc>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: cpu@0 {
  19. compatible = "qcom,krait";
  20. enable-method = "qcom,kpss-acc-v1";
  21. device_type = "cpu";
  22. reg = <0>;
  23. next-level-cache = <&L2>;
  24. qcom,acc = <&acc0>;
  25. qcom,saw = <&saw0>;
  26. clocks = <&kraitcc 0>, <&kraitcc 4>;
  27. clock-names = "cpu", "l2";
  28. clock-latency = <100000>;
  29. cpu-supply = <&smb208_s2a>;
  30. voltage-tolerance = <5>;
  31. cooling-min-state = <0>;
  32. cooling-max-state = <10>;
  33. #cooling-cells = <2>;
  34. cpu-idle-states = <&CPU_SPC>;
  35. };
  36. cpu1: cpu@1 {
  37. compatible = "qcom,krait";
  38. enable-method = "qcom,kpss-acc-v1";
  39. device_type = "cpu";
  40. reg = <1>;
  41. next-level-cache = <&L2>;
  42. qcom,acc = <&acc1>;
  43. qcom,saw = <&saw1>;
  44. clocks = <&kraitcc 1>, <&kraitcc 4>;
  45. clock-names = "cpu", "l2";
  46. clock-latency = <100000>;
  47. cpu-supply = <&smb208_s2b>;
  48. cooling-min-state = <0>;
  49. cooling-max-state = <10>;
  50. #cooling-cells = <2>;
  51. cpu-idle-states = <&CPU_SPC>;
  52. };
  53. L2: l2-cache {
  54. compatible = "cache";
  55. cache-level = <2>;
  56. qcom,saw = <&saw_l2>;
  57. };
  58. qcom,l2 {
  59. qcom,l2-rates = <384000000 1000000000 1200000000>;
  60. };
  61. idle-states {
  62. CPU_SPC: spc {
  63. compatible = "qcom,idle-state-spc",
  64. "arm,idle-state";
  65. entry-latency-us = <400>;
  66. exit-latency-us = <900>;
  67. min-residency-us = <3000>;
  68. };
  69. };
  70. };
  71. thermal-zones {
  72. tsens_tz_sensor0 {
  73. polling-delay-passive = <0>;
  74. polling-delay = <0>;
  75. thermal-sensors = <&tsens 0>;
  76. trips {
  77. cpu-critical-hi {
  78. temperature = <125000>;
  79. hysteresis = <2000>;
  80. type = "critical_high";
  81. };
  82. cpu-config-hi {
  83. temperature = <105000>;
  84. hysteresis = <2000>;
  85. type = "configurable_hi";
  86. };
  87. cpu-config-lo {
  88. temperature = <95000>;
  89. hysteresis = <2000>;
  90. type = "configurable_lo";
  91. };
  92. cpu-critical-low {
  93. temperature = <0>;
  94. hysteresis = <2000>;
  95. type = "critical_low";
  96. };
  97. };
  98. };
  99. tsens_tz_sensor1 {
  100. polling-delay-passive = <0>;
  101. polling-delay = <0>;
  102. thermal-sensors = <&tsens 1>;
  103. trips {
  104. cpu-critical-hi {
  105. temperature = <125000>;
  106. hysteresis = <2000>;
  107. type = "critical_high";
  108. };
  109. cpu-config-hi {
  110. temperature = <105000>;
  111. hysteresis = <2000>;
  112. type = "configurable_hi";
  113. };
  114. cpu-config-lo {
  115. temperature = <95000>;
  116. hysteresis = <2000>;
  117. type = "configurable_lo";
  118. };
  119. cpu-critical-low {
  120. temperature = <0>;
  121. hysteresis = <2000>;
  122. type = "critical_low";
  123. };
  124. };
  125. };
  126. tsens_tz_sensor2 {
  127. polling-delay-passive = <0>;
  128. polling-delay = <0>;
  129. thermal-sensors = <&tsens 2>;
  130. trips {
  131. cpu-critical-hi {
  132. temperature = <125000>;
  133. hysteresis = <2000>;
  134. type = "critical_high";
  135. };
  136. cpu-config-hi {
  137. temperature = <105000>;
  138. hysteresis = <2000>;
  139. type = "configurable_hi";
  140. };
  141. cpu-config-lo {
  142. temperature = <95000>;
  143. hysteresis = <2000>;
  144. type = "configurable_lo";
  145. };
  146. cpu-critical-low {
  147. temperature = <0>;
  148. hysteresis = <2000>;
  149. type = "critical_low";
  150. };
  151. };
  152. };
  153. tsens_tz_sensor3 {
  154. polling-delay-passive = <0>;
  155. polling-delay = <0>;
  156. thermal-sensors = <&tsens 3>;
  157. trips {
  158. cpu-critical-hi {
  159. temperature = <125000>;
  160. hysteresis = <2000>;
  161. type = "critical_high";
  162. };
  163. cpu-config-hi {
  164. temperature = <105000>;
  165. hysteresis = <2000>;
  166. type = "configurable_hi";
  167. };
  168. cpu-config-lo {
  169. temperature = <95000>;
  170. hysteresis = <2000>;
  171. type = "configurable_lo";
  172. };
  173. cpu-critical-low {
  174. temperature = <0>;
  175. hysteresis = <2000>;
  176. type = "critical_low";
  177. };
  178. };
  179. };
  180. tsens_tz_sensor4 {
  181. polling-delay-passive = <0>;
  182. polling-delay = <0>;
  183. thermal-sensors = <&tsens 4>;
  184. trips {
  185. cpu-critical-hi {
  186. temperature = <125000>;
  187. hysteresis = <2000>;
  188. type = "critical_high";
  189. };
  190. cpu-config-hi {
  191. temperature = <105000>;
  192. hysteresis = <2000>;
  193. type = "configurable_hi";
  194. };
  195. cpu-config-lo {
  196. temperature = <95000>;
  197. hysteresis = <2000>;
  198. type = "configurable_lo";
  199. };
  200. cpu-critical-low {
  201. temperature = <0>;
  202. hysteresis = <2000>;
  203. type = "critical_low";
  204. };
  205. };
  206. };
  207. tsens_tz_sensor5 {
  208. polling-delay-passive = <0>;
  209. polling-delay = <0>;
  210. thermal-sensors = <&tsens 5>;
  211. trips {
  212. cpu-critical-hi {
  213. temperature = <125000>;
  214. hysteresis = <2000>;
  215. type = "critical_high";
  216. };
  217. cpu-config-hi {
  218. temperature = <105000>;
  219. hysteresis = <2000>;
  220. type = "configurable_hi";
  221. };
  222. cpu-config-lo {
  223. temperature = <95000>;
  224. hysteresis = <2000>;
  225. type = "configurable_lo";
  226. };
  227. cpu-critical-low {
  228. temperature = <0>;
  229. hysteresis = <2000>;
  230. type = "critical_low";
  231. };
  232. };
  233. };
  234. tsens_tz_sensor6 {
  235. polling-delay-passive = <0>;
  236. polling-delay = <0>;
  237. thermal-sensors = <&tsens 6>;
  238. trips {
  239. cpu-critical-hi {
  240. temperature = <125000>;
  241. hysteresis = <2000>;
  242. type = "critical_high";
  243. };
  244. cpu-config-hi {
  245. temperature = <105000>;
  246. hysteresis = <2000>;
  247. type = "configurable_hi";
  248. };
  249. cpu-config-lo {
  250. temperature = <95000>;
  251. hysteresis = <2000>;
  252. type = "configurable_lo";
  253. };
  254. cpu-critical-low {
  255. temperature = <0>;
  256. hysteresis = <2000>;
  257. type = "critical_low";
  258. };
  259. };
  260. };
  261. tsens_tz_sensor7 {
  262. polling-delay-passive = <0>;
  263. polling-delay = <0>;
  264. thermal-sensors = <&tsens 7>;
  265. trips {
  266. cpu-critical-hi {
  267. temperature = <125000>;
  268. hysteresis = <2000>;
  269. type = "critical_high";
  270. };
  271. cpu-config-hi {
  272. temperature = <105000>;
  273. hysteresis = <2000>;
  274. type = "configurable_hi";
  275. };
  276. cpu-config-lo {
  277. temperature = <95000>;
  278. hysteresis = <2000>;
  279. type = "configurable_lo";
  280. };
  281. cpu-critical-low {
  282. temperature = <0>;
  283. hysteresis = <2000>;
  284. type = "critical_low";
  285. };
  286. };
  287. };
  288. tsens_tz_sensor8 {
  289. polling-delay-passive = <0>;
  290. polling-delay = <0>;
  291. thermal-sensors = <&tsens 8>;
  292. trips {
  293. cpu-critical-hi {
  294. temperature = <125000>;
  295. hysteresis = <2000>;
  296. type = "critical_high";
  297. };
  298. cpu-config-hi {
  299. temperature = <105000>;
  300. hysteresis = <2000>;
  301. type = "configurable_hi";
  302. };
  303. cpu-config-lo {
  304. temperature = <95000>;
  305. hysteresis = <2000>;
  306. type = "configurable_lo";
  307. };
  308. cpu-critical-low {
  309. temperature = <0>;
  310. hysteresis = <2000>;
  311. type = "critical_low";
  312. };
  313. };
  314. };
  315. tsens_tz_sensor9 {
  316. polling-delay-passive = <0>;
  317. polling-delay = <0>;
  318. thermal-sensors = <&tsens 9>;
  319. trips {
  320. cpu-critical-hi {
  321. temperature = <125000>;
  322. hysteresis = <2000>;
  323. type = "critical_high";
  324. };
  325. cpu-config-hi {
  326. temperature = <105000>;
  327. hysteresis = <2000>;
  328. type = "configurable_hi";
  329. };
  330. cpu-config-lo {
  331. temperature = <95000>;
  332. hysteresis = <2000>;
  333. type = "configurable_lo";
  334. };
  335. cpu-critical-low {
  336. temperature = <0>;
  337. hysteresis = <2000>;
  338. type = "critical_low";
  339. };
  340. };
  341. };
  342. tsens_tz_sensor10 {
  343. polling-delay-passive = <0>;
  344. polling-delay = <0>;
  345. thermal-sensors = <&tsens 10>;
  346. trips {
  347. cpu-critical-hi {
  348. temperature = <125000>;
  349. hysteresis = <2000>;
  350. type = "critical_high";
  351. };
  352. cpu-config-hi {
  353. temperature = <105000>;
  354. hysteresis = <2000>;
  355. type = "configurable_hi";
  356. };
  357. cpu-config-lo {
  358. temperature = <95000>;
  359. hysteresis = <2000>;
  360. type = "configurable_lo";
  361. };
  362. cpu-critical-low {
  363. temperature = <0>;
  364. hysteresis = <2000>;
  365. type = "critical_low";
  366. };
  367. };
  368. };
  369. };
  370. cpu-pmu {
  371. compatible = "qcom,krait-pmu";
  372. interrupts = <1 10 0x304>;
  373. };
  374. reserved-memory {
  375. #address-cells = <1>;
  376. #size-cells = <1>;
  377. ranges;
  378. nss@40000000 {
  379. reg = <0x40000000 0x1000000>;
  380. no-map;
  381. };
  382. smem: smem@41000000 {
  383. reg = <0x41000000 0x200000>;
  384. no-map;
  385. };
  386. };
  387. clocks {
  388. cxo_board {
  389. compatible = "fixed-clock";
  390. #clock-cells = <0>;
  391. clock-frequency = <25000000>;
  392. };
  393. pxo_board {
  394. compatible = "fixed-clock";
  395. #clock-cells = <0>;
  396. clock-frequency = <25000000>;
  397. };
  398. sleep_clk: sleep_clk {
  399. compatible = "fixed-clock";
  400. clock-frequency = <32768>;
  401. #clock-cells = <0>;
  402. };
  403. };
  404. firmware {
  405. scm {
  406. compatible = "qcom,scm-ipq806x";
  407. };
  408. };
  409. kraitcc: clock-controller {
  410. compatible = "qcom,krait-cc-v1";
  411. #clock-cells = <1>;
  412. };
  413. qcom,pvs {
  414. qcom,pvs-format-a;
  415. qcom,speed0-pvs0-bin-v0 =
  416. < 1400000000 1250000 >,
  417. < 1200000000 1200000 >,
  418. < 1000000000 1150000 >,
  419. < 800000000 1100000 >,
  420. < 600000000 1050000 >,
  421. < 384000000 1000000 >;
  422. qcom,speed0-pvs1-bin-v0 =
  423. < 1400000000 1175000 >,
  424. < 1200000000 1125000 >,
  425. < 1000000000 1075000 >,
  426. < 800000000 1025000 >,
  427. < 600000000 975000 >,
  428. < 384000000 925000 >;
  429. qcom,speed0-pvs2-bin-v0 =
  430. < 1400000000 1125000 >,
  431. < 1200000000 1075000 >,
  432. < 1000000000 1025000 >,
  433. < 800000000 995000 >,
  434. < 600000000 925000 >,
  435. < 384000000 875000 >;
  436. qcom,speed0-pvs3-bin-v0 =
  437. < 1400000000 1050000 >,
  438. < 1200000000 1000000 >,
  439. < 1000000000 950000 >,
  440. < 800000000 900000 >,
  441. < 600000000 850000 >,
  442. < 384000000 800000 >;
  443. };
  444. soc: soc {
  445. #address-cells = <1>;
  446. #size-cells = <1>;
  447. ranges;
  448. compatible = "simple-bus";
  449. lpass@28100000 {
  450. compatible = "qcom,lpass-cpu";
  451. status = "disabled";
  452. clocks = <&lcc AHBIX_CLK>,
  453. <&lcc MI2S_OSR_CLK>,
  454. <&lcc MI2S_BIT_CLK>;
  455. clock-names = "ahbix-clk",
  456. "mi2s-osr-clk",
  457. "mi2s-bit-clk";
  458. interrupts = <0 85 1>;
  459. interrupt-names = "lpass-irq-lpaif";
  460. reg = <0x28100000 0x10000>;
  461. reg-names = "lpass-lpaif";
  462. };
  463. qfprom: qfprom@700000 {
  464. compatible = "qcom,qfprom", "syscon";
  465. reg = <0x700000 0x1000>;
  466. #address-cells = <1>;
  467. #size-cells = <1>;
  468. status = "okay";
  469. tsens_calib: calib@400 {
  470. reg = <0x400 0x10>;
  471. };
  472. tsens_backup: backup@410 {
  473. reg = <0x410 0x10>;
  474. };
  475. };
  476. rpm@108000 {
  477. compatible = "qcom,rpm-ipq8064";
  478. reg = <0x108000 0x1000>;
  479. qcom,ipc = <&l2cc 0x8 2>;
  480. interrupts = <0 19 0>,
  481. <0 21 0>,
  482. <0 22 0>;
  483. interrupt-names = "ack",
  484. "err",
  485. "wakeup";
  486. clocks = <&gcc RPM_MSG_RAM_H_CLK>;
  487. clock-names = "ram";
  488. #address-cells = <1>;
  489. #size-cells = <0>;
  490. rpmcc: clock-controller {
  491. compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
  492. #clock-cells = <1>;
  493. };
  494. regulators {
  495. compatible = "qcom,rpm-smb208-regulators";
  496. smb208_s1a: s1a {
  497. regulator-min-microvolt = <1050000>;
  498. regulator-max-microvolt = <1150000>;
  499. qcom,switch-mode-frequency = <1200000>;
  500. };
  501. smb208_s1b: s1b {
  502. regulator-min-microvolt = <1050000>;
  503. regulator-max-microvolt = <1150000>;
  504. qcom,switch-mode-frequency = <1200000>;
  505. };
  506. smb208_s2a: s2a {
  507. regulator-min-microvolt = < 800000>;
  508. regulator-max-microvolt = <1250000>;
  509. qcom,switch-mode-frequency = <1200000>;
  510. };
  511. smb208_s2b: s2b {
  512. regulator-min-microvolt = < 800000>;
  513. regulator-max-microvolt = <1250000>;
  514. qcom,switch-mode-frequency = <1200000>;
  515. };
  516. };
  517. };
  518. rng@1a500000 {
  519. compatible = "qcom,prng";
  520. reg = <0x1a500000 0x200>;
  521. clocks = <&gcc PRNG_CLK>;
  522. clock-names = "core";
  523. };
  524. qcom_pinmux: pinmux@800000 {
  525. compatible = "qcom,ipq8064-pinctrl";
  526. reg = <0x800000 0x4000>;
  527. gpio-controller;
  528. #gpio-cells = <2>;
  529. interrupt-controller;
  530. #interrupt-cells = <2>;
  531. interrupts = <0 16 0x4>;
  532. pcie0_pins: pcie0_pinmux {
  533. mux {
  534. pins = "gpio3";
  535. function = "pcie1_rst";
  536. drive-strength = <2>;
  537. bias-disable;
  538. };
  539. };
  540. pcie1_pins: pcie1_pinmux {
  541. mux {
  542. pins = "gpio48";
  543. function = "pcie2_rst";
  544. drive-strength = <2>;
  545. bias-disable;
  546. };
  547. };
  548. pcie2_pins: pcie2_pinmux {
  549. mux {
  550. pins = "gpio63";
  551. function = "pcie3_rst";
  552. drive-strength = <2>;
  553. bias-disable;
  554. output-low;
  555. };
  556. };
  557. };
  558. intc: interrupt-controller@2000000 {
  559. compatible = "qcom,msm-qgic2";
  560. interrupt-controller;
  561. #interrupt-cells = <3>;
  562. reg = <0x02000000 0x1000>,
  563. <0x02002000 0x1000>;
  564. };
  565. timer@200a000 {
  566. compatible = "qcom,kpss-timer", "qcom,msm-timer";
  567. interrupts = <1 1 0x301>,
  568. <1 2 0x301>,
  569. <1 3 0x301>,
  570. <1 4 0x301>,
  571. <1 5 0x301>;
  572. reg = <0x0200a000 0x100>;
  573. clock-frequency = <25000000>,
  574. <32768>;
  575. clocks = <&sleep_clk>;
  576. clock-names = "sleep";
  577. cpu-offset = <0x80000>;
  578. };
  579. acc0: clock-controller@2088000 {
  580. compatible = "qcom,kpss-acc-v1";
  581. reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  582. clock-output-names = "acpu0_aux";
  583. };
  584. acc1: clock-controller@2098000 {
  585. compatible = "qcom,kpss-acc-v1";
  586. reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  587. clock-output-names = "acpu1_aux";
  588. };
  589. l2cc: clock-controller@2011000 {
  590. compatible = "qcom,kpss-gcc", "syscon";
  591. reg = <0x2011000 0x1000>;
  592. clock-output-names = "acpu_l2_aux";
  593. };
  594. saw0: regulator@2089000 {
  595. compatible = "qcom,saw2", "syscon";
  596. reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  597. regulator;
  598. };
  599. saw1: regulator@2099000 {
  600. compatible = "qcom,saw2", "syscon";
  601. reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  602. regulator;
  603. };
  604. saw_l2: regulator@02012000 {
  605. compatible = "qcom,saw2", "syscon";
  606. reg = <0x02012000 0x1000>;
  607. regulator;
  608. };
  609. sic_non_secure: sic-non-secure@12100000 {
  610. compatible = "syscon";
  611. reg = <0x12100000 0x10000>;
  612. };
  613. gsbi2: gsbi@12480000 {
  614. compatible = "qcom,gsbi-v1.0.0";
  615. cell-index = <2>;
  616. reg = <0x12480000 0x100>;
  617. clocks = <&gcc GSBI2_H_CLK>;
  618. clock-names = "iface";
  619. #address-cells = <1>;
  620. #size-cells = <1>;
  621. ranges;
  622. status = "disabled";
  623. syscon-tcsr = <&tcsr>;
  624. uart2: serial@12490000 {
  625. compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  626. reg = <0x12490000 0x1000>,
  627. <0x12480000 0x1000>;
  628. interrupts = <0 195 0x0>;
  629. clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
  630. clock-names = "core", "iface";
  631. status = "disabled";
  632. };
  633. i2c@124a0000 {
  634. compatible = "qcom,i2c-qup-v1.1.1";
  635. reg = <0x124a0000 0x1000>;
  636. interrupts = <0 196 0>;
  637. clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
  638. clock-names = "core", "iface";
  639. status = "disabled";
  640. #address-cells = <1>;
  641. #size-cells = <0>;
  642. };
  643. };
  644. gsbi4: gsbi@16300000 {
  645. compatible = "qcom,gsbi-v1.0.0";
  646. cell-index = <4>;
  647. reg = <0x16300000 0x100>;
  648. clocks = <&gcc GSBI4_H_CLK>;
  649. clock-names = "iface";
  650. #address-cells = <1>;
  651. #size-cells = <1>;
  652. ranges;
  653. status = "disabled";
  654. syscon-tcsr = <&tcsr>;
  655. gsbi4_serial: serial@16340000 {
  656. compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  657. reg = <0x16340000 0x1000>,
  658. <0x16300000 0x1000>;
  659. interrupts = <0 152 0x0>;
  660. clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
  661. clock-names = "core", "iface";
  662. status = "disabled";
  663. };
  664. i2c@16380000 {
  665. compatible = "qcom,i2c-qup-v1.1.1";
  666. reg = <0x16380000 0x1000>;
  667. interrupts = <0 153 0>;
  668. clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
  669. clock-names = "core", "iface";
  670. status = "disabled";
  671. #address-cells = <1>;
  672. #size-cells = <0>;
  673. };
  674. };
  675. gsbi5: gsbi@1a200000 {
  676. compatible = "qcom,gsbi-v1.0.0";
  677. cell-index = <5>;
  678. reg = <0x1a200000 0x100>;
  679. clocks = <&gcc GSBI5_H_CLK>;
  680. clock-names = "iface";
  681. #address-cells = <1>;
  682. #size-cells = <1>;
  683. ranges;
  684. status = "disabled";
  685. syscon-tcsr = <&tcsr>;
  686. uart5: serial@1a240000 {
  687. compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  688. reg = <0x1a240000 0x1000>,
  689. <0x1a200000 0x1000>;
  690. interrupts = <0 154 0x0>;
  691. clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
  692. clock-names = "core", "iface";
  693. status = "disabled";
  694. };
  695. i2c@1a280000 {
  696. compatible = "qcom,i2c-qup-v1.1.1";
  697. reg = <0x1a280000 0x1000>;
  698. interrupts = <0 155 0>;
  699. clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
  700. clock-names = "core", "iface";
  701. status = "disabled";
  702. #address-cells = <1>;
  703. #size-cells = <0>;
  704. };
  705. spi@1a280000 {
  706. compatible = "qcom,spi-qup-v1.1.1";
  707. reg = <0x1a280000 0x1000>;
  708. interrupts = <0 155 0>;
  709. clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
  710. clock-names = "core", "iface";
  711. status = "disabled";
  712. #address-cells = <1>;
  713. #size-cells = <0>;
  714. };
  715. };
  716. sata_phy: sata-phy@1b400000 {
  717. compatible = "qcom,ipq806x-sata-phy";
  718. reg = <0x1b400000 0x200>;
  719. clocks = <&gcc SATA_PHY_CFG_CLK>;
  720. clock-names = "cfg";
  721. #phy-cells = <0>;
  722. status = "disabled";
  723. };
  724. sata@29000000 {
  725. compatible = "qcom,ipq806x-ahci", "generic-ahci";
  726. reg = <0x29000000 0x180>;
  727. ports-implemented = <0x1>;
  728. interrupts = <0 209 0x0>;
  729. clocks = <&gcc SFAB_SATA_S_H_CLK>,
  730. <&gcc SATA_H_CLK>,
  731. <&gcc SATA_A_CLK>,
  732. <&gcc SATA_RXOOB_CLK>,
  733. <&gcc SATA_PMALIVE_CLK>;
  734. clock-names = "slave_face", "iface", "core",
  735. "rxoob", "pmalive";
  736. assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
  737. assigned-clock-rates = <100000000>, <100000000>;
  738. phys = <&sata_phy>;
  739. phy-names = "sata-phy";
  740. status = "disabled";
  741. };
  742. qcom,ssbi@500000 {
  743. compatible = "qcom,ssbi";
  744. reg = <0x00500000 0x1000>;
  745. qcom,controller-type = "pmic-arbiter";
  746. };
  747. gcc: clock-controller@900000 {
  748. compatible = "qcom,gcc-ipq8064";
  749. reg = <0x00900000 0x4000>;
  750. #clock-cells = <1>;
  751. #reset-cells = <1>;
  752. #power-domain-cells = <1>;
  753. };
  754. tsens: thermal-sensor@900000 {
  755. compatible = "qcom,ipq8064-tsens";
  756. reg = <0x900000 0x3680>;
  757. nvmem-cells = <&tsens_calib>, <&tsens_backup>;
  758. nvmem-cell-names = "calib", "calib_backup";
  759. interrupts = <0 178 0>;
  760. #thermal-sensor-cells = <1>;
  761. };
  762. tcsr: syscon@1a400000 {
  763. compatible = "qcom,tcsr-ipq8064", "syscon";
  764. reg = <0x1a400000 0x100>;
  765. };
  766. lcc: clock-controller@28000000 {
  767. compatible = "qcom,lcc-ipq8064";
  768. reg = <0x28000000 0x1000>;
  769. #clock-cells = <1>;
  770. #reset-cells = <1>;
  771. };
  772. sfpb_mutex_block: syscon@1200600 {
  773. compatible = "syscon";
  774. reg = <0x01200600 0x100>;
  775. };
  776. hs_phy_1: phy@100f8800 {
  777. compatible = "qcom,dwc3-hs-usb-phy";
  778. reg = <0x100f8800 0x30>;
  779. clocks = <&gcc USB30_1_UTMI_CLK>;
  780. clock-names = "ref";
  781. #phy-cells = <0>;
  782. status = "disabled";
  783. };
  784. ss_phy_1: phy@100f8830 {
  785. compatible = "qcom,dwc3-ss-usb-phy";
  786. reg = <0x100f8830 0x30>;
  787. clocks = <&gcc USB30_1_MASTER_CLK>;
  788. clock-names = "ref";
  789. #phy-cells = <0>;
  790. status = "disabled";
  791. };
  792. hs_phy_0: phy@110f8800 {
  793. compatible = "qcom,dwc3-hs-usb-phy";
  794. reg = <0x110f8800 0x30>;
  795. clocks = <&gcc USB30_0_UTMI_CLK>;
  796. clock-names = "ref";
  797. #phy-cells = <0>;
  798. status = "disabled";
  799. };
  800. ss_phy_0: phy@110f8830 {
  801. compatible = "qcom,dwc3-ss-usb-phy";
  802. reg = <0x110f8830 0x30>;
  803. clocks = <&gcc USB30_0_MASTER_CLK>;
  804. clock-names = "ref";
  805. #phy-cells = <0>;
  806. status = "disabled";
  807. };
  808. usb3_0: usb30@0 {
  809. compatible = "qcom,dwc3";
  810. #address-cells = <1>;
  811. #size-cells = <1>;
  812. clocks = <&gcc USB30_0_MASTER_CLK>;
  813. clock-names = "core";
  814. ranges;
  815. resets = <&gcc USB30_0_MASTER_RESET>;
  816. reset-names = "usb30_0_mstr_rst";
  817. status = "disabled";
  818. dwc3_0: dwc3@11000000 {
  819. compatible = "snps,dwc3";
  820. reg = <0x11000000 0xcd00>;
  821. interrupts = <0 110 0x4>;
  822. phys = <&hs_phy_0>, <&ss_phy_0>;
  823. phy-names = "usb2-phy", "usb3-phy";
  824. dr_mode = "host";
  825. snps,dis_u3_susphy_quirk;
  826. };
  827. };
  828. usb3_1: usb30@1 {
  829. compatible = "qcom,dwc3";
  830. #address-cells = <1>;
  831. #size-cells = <1>;
  832. clocks = <&gcc USB30_1_MASTER_CLK>;
  833. clock-names = "core";
  834. ranges;
  835. resets = <&gcc USB30_1_MASTER_RESET>;
  836. reset-names = "usb30_1_mstr_rst";
  837. status = "disabled";
  838. dwc3_1: dwc3@10000000 {
  839. compatible = "snps,dwc3";
  840. reg = <0x10000000 0xcd00>;
  841. interrupts = <0 205 0x4>;
  842. phys = <&hs_phy_1>, <&ss_phy_1>;
  843. phy-names = "usb2-phy", "usb3-phy";
  844. dr_mode = "host";
  845. snps,dis_u3_susphy_quirk;
  846. };
  847. };
  848. pcie0: pci@1b500000 {
  849. compatible = "qcom,pcie-ipq8064";
  850. reg = <0x1b500000 0x1000
  851. 0x1b502000 0x80
  852. 0x1b600000 0x100
  853. 0x0ff00000 0x100000>;
  854. reg-names = "dbi", "elbi", "parf", "config";
  855. device_type = "pci";
  856. linux,pci-domain = <0>;
  857. bus-range = <0x00 0xff>;
  858. num-lanes = <1>;
  859. #address-cells = <3>;
  860. #size-cells = <2>;
  861. ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
  862. 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
  863. interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
  864. interrupt-names = "msi";
  865. #interrupt-cells = <1>;
  866. interrupt-map-mask = <0 0 0 0x7>;
  867. interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  868. <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  869. <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  870. <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  871. clocks = <&gcc PCIE_A_CLK>,
  872. <&gcc PCIE_H_CLK>,
  873. <&gcc PCIE_PHY_CLK>,
  874. <&gcc PCIE_AUX_CLK>,
  875. <&gcc PCIE_ALT_REF_CLK>;
  876. clock-names = "core", "iface", "phy", "aux", "ref";
  877. assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
  878. assigned-clock-rates = <100000000>;
  879. resets = <&gcc PCIE_ACLK_RESET>,
  880. <&gcc PCIE_HCLK_RESET>,
  881. <&gcc PCIE_POR_RESET>,
  882. <&gcc PCIE_PCI_RESET>,
  883. <&gcc PCIE_PHY_RESET>,
  884. <&gcc PCIE_EXT_RESET>;
  885. reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  886. pinctrl-0 = <&pcie0_pins>;
  887. pinctrl-names = "default";
  888. perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
  889. phy-tx0-term-offset = <7>;
  890. status = "disabled";
  891. };
  892. pcie1: pci@1b700000 {
  893. compatible = "qcom,pcie-ipq8064";
  894. reg = <0x1b700000 0x1000
  895. 0x1b702000 0x80
  896. 0x1b800000 0x100
  897. 0x31f00000 0x100000>;
  898. reg-names = "dbi", "elbi", "parf", "config";
  899. device_type = "pci";
  900. linux,pci-domain = <1>;
  901. bus-range = <0x00 0xff>;
  902. num-lanes = <1>;
  903. #address-cells = <3>;
  904. #size-cells = <2>;
  905. ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
  906. 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
  907. interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
  908. interrupt-names = "msi";
  909. #interrupt-cells = <1>;
  910. interrupt-map-mask = <0 0 0 0x7>;
  911. interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  912. <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  913. <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  914. <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  915. clocks = <&gcc PCIE_1_A_CLK>,
  916. <&gcc PCIE_1_H_CLK>,
  917. <&gcc PCIE_1_PHY_CLK>,
  918. <&gcc PCIE_1_AUX_CLK>,
  919. <&gcc PCIE_1_ALT_REF_CLK>;
  920. clock-names = "core", "iface", "phy", "aux", "ref";
  921. assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
  922. assigned-clock-rates = <100000000>;
  923. resets = <&gcc PCIE_1_ACLK_RESET>,
  924. <&gcc PCIE_1_HCLK_RESET>,
  925. <&gcc PCIE_1_POR_RESET>,
  926. <&gcc PCIE_1_PCI_RESET>,
  927. <&gcc PCIE_1_PHY_RESET>,
  928. <&gcc PCIE_1_EXT_RESET>;
  929. reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  930. pinctrl-0 = <&pcie1_pins>;
  931. pinctrl-names = "default";
  932. perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
  933. phy-tx0-term-offset = <7>;
  934. status = "disabled";
  935. };
  936. pcie2: pci@1b900000 {
  937. compatible = "qcom,pcie-ipq8064";
  938. reg = <0x1b900000 0x1000
  939. 0x1b902000 0x80
  940. 0x1ba00000 0x100
  941. 0x35f00000 0x100000>;
  942. reg-names = "dbi", "elbi", "parf", "config";
  943. device_type = "pci";
  944. linux,pci-domain = <2>;
  945. bus-range = <0x00 0xff>;
  946. num-lanes = <1>;
  947. #address-cells = <3>;
  948. #size-cells = <2>;
  949. ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
  950. 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
  951. interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
  952. interrupt-names = "msi";
  953. #interrupt-cells = <1>;
  954. interrupt-map-mask = <0 0 0 0x7>;
  955. interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  956. <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  957. <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  958. <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  959. clocks = <&gcc PCIE_2_A_CLK>,
  960. <&gcc PCIE_2_H_CLK>,
  961. <&gcc PCIE_2_PHY_CLK>,
  962. <&gcc PCIE_2_AUX_CLK>,
  963. <&gcc PCIE_2_ALT_REF_CLK>;
  964. clock-names = "core", "iface", "phy", "aux", "ref";
  965. assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
  966. assigned-clock-rates = <100000000>;
  967. resets = <&gcc PCIE_2_ACLK_RESET>,
  968. <&gcc PCIE_2_HCLK_RESET>,
  969. <&gcc PCIE_2_POR_RESET>,
  970. <&gcc PCIE_2_PCI_RESET>,
  971. <&gcc PCIE_2_PHY_RESET>,
  972. <&gcc PCIE_2_EXT_RESET>;
  973. reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  974. pinctrl-0 = <&pcie2_pins>;
  975. pinctrl-names = "default";
  976. perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
  977. phy-tx0-term-offset = <7>;
  978. status = "disabled";
  979. };
  980. adm_dma: dma@18300000 {
  981. compatible = "qcom,adm";
  982. reg = <0x18300000 0x100000>;
  983. interrupts = <0 170 0>;
  984. #dma-cells = <1>;
  985. clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
  986. clock-names = "core", "iface";
  987. resets = <&gcc ADM0_RESET>,
  988. <&gcc ADM0_PBUS_RESET>,
  989. <&gcc ADM0_C0_RESET>,
  990. <&gcc ADM0_C1_RESET>,
  991. <&gcc ADM0_C2_RESET>;
  992. reset-names = "clk", "pbus", "c0", "c1", "c2";
  993. qcom,ee = <0>;
  994. status = "disabled";
  995. };
  996. nand@1ac00000 {
  997. compatible = "qcom,ipq806x-nand";
  998. reg = <0x1ac00000 0x800>;
  999. clocks = <&gcc EBI2_CLK>,
  1000. <&gcc EBI2_AON_CLK>;
  1001. clock-names = "core", "aon";
  1002. dmas = <&adm_dma 3>;
  1003. dma-names = "rxtx";
  1004. qcom,cmd-crci = <15>;
  1005. qcom,data-crci = <3>;
  1006. status = "disabled";
  1007. #address-cells = <1>;
  1008. #size-cells = <0>;
  1009. };
  1010. nss_common: syscon@03000000 {
  1011. compatible = "syscon";
  1012. reg = <0x03000000 0x0000FFFF>;
  1013. };
  1014. qsgmii_csr: syscon@1bb00000 {
  1015. compatible = "syscon";
  1016. reg = <0x1bb00000 0x000001FF>;
  1017. };
  1018. stmmac_axi_setup: stmmac-axi-config {
  1019. snps,wr_osr_lmt = <7>;
  1020. snps,rd_osr_lmt = <7>;
  1021. snps,blen = <16 0 0 0 0 0 0>;
  1022. };
  1023. gmac0: ethernet@37000000 {
  1024. device_type = "network";
  1025. compatible = "qcom,ipq806x-gmac";
  1026. reg = <0x37000000 0x200000>;
  1027. interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
  1028. interrupt-names = "macirq";
  1029. snps,axi-config = <&stmmac_axi_setup>;
  1030. snps,pbl = <32>;
  1031. snps,aal = <1>;
  1032. qcom,nss-common = <&nss_common>;
  1033. qcom,qsgmii-csr = <&qsgmii_csr>;
  1034. clocks = <&gcc GMAC_CORE1_CLK>;
  1035. clock-names = "stmmaceth";
  1036. resets = <&gcc GMAC_CORE1_RESET>;
  1037. reset-names = "stmmaceth";
  1038. status = "disabled";
  1039. };
  1040. gmac1: ethernet@37200000 {
  1041. device_type = "network";
  1042. compatible = "qcom,ipq806x-gmac";
  1043. reg = <0x37200000 0x200000>;
  1044. interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
  1045. interrupt-names = "macirq";
  1046. snps,axi-config = <&stmmac_axi_setup>;
  1047. snps,pbl = <32>;
  1048. snps,aal = <1>;
  1049. qcom,nss-common = <&nss_common>;
  1050. qcom,qsgmii-csr = <&qsgmii_csr>;
  1051. clocks = <&gcc GMAC_CORE2_CLK>;
  1052. clock-names = "stmmaceth";
  1053. resets = <&gcc GMAC_CORE2_RESET>;
  1054. reset-names = "stmmaceth";
  1055. status = "disabled";
  1056. };
  1057. gmac2: ethernet@37400000 {
  1058. device_type = "network";
  1059. compatible = "qcom,ipq806x-gmac";
  1060. reg = <0x37400000 0x200000>;
  1061. interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
  1062. interrupt-names = "macirq";
  1063. snps,axi-config = <&stmmac_axi_setup>;
  1064. snps,pbl = <32>;
  1065. snps,aal = <1>;
  1066. qcom,nss-common = <&nss_common>;
  1067. qcom,qsgmii-csr = <&qsgmii_csr>;
  1068. clocks = <&gcc GMAC_CORE3_CLK>;
  1069. clock-names = "stmmaceth";
  1070. resets = <&gcc GMAC_CORE3_RESET>;
  1071. reset-names = "stmmaceth";
  1072. status = "disabled";
  1073. };
  1074. gmac3: ethernet@37600000 {
  1075. device_type = "network";
  1076. compatible = "qcom,ipq806x-gmac";
  1077. reg = <0x37600000 0x200000>;
  1078. interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
  1079. interrupt-names = "macirq";
  1080. snps,axi-config = <&stmmac_axi_setup>;
  1081. snps,pbl = <32>;
  1082. snps,aal = <1>;
  1083. qcom,nss-common = <&nss_common>;
  1084. qcom,qsgmii-csr = <&qsgmii_csr>;
  1085. clocks = <&gcc GMAC_CORE4_CLK>;
  1086. clock-names = "stmmaceth";
  1087. resets = <&gcc GMAC_CORE4_RESET>;
  1088. reset-names = "stmmaceth";
  1089. status = "disabled";
  1090. };
  1091. /* Temporary fixed regulator */
  1092. vsdcc_fixed: vsdcc-regulator {
  1093. compatible = "regulator-fixed";
  1094. regulator-name = "SDCC Power";
  1095. regulator-min-microvolt = <3300000>;
  1096. regulator-max-microvolt = <3300000>;
  1097. regulator-always-on;
  1098. };
  1099. sdcc1bam:dma@12402000 {
  1100. compatible = "qcom,bam-v1.3.0";
  1101. reg = <0x12402000 0x8000>;
  1102. interrupts = <0 98 0>;
  1103. clocks = <&gcc SDC1_H_CLK>;
  1104. clock-names = "bam_clk";
  1105. #dma-cells = <1>;
  1106. qcom,ee = <0>;
  1107. };
  1108. sdcc3bam:dma@12182000 {
  1109. compatible = "qcom,bam-v1.3.0";
  1110. reg = <0x12182000 0x8000>;
  1111. interrupts = <0 96 0>;
  1112. clocks = <&gcc SDC3_H_CLK>;
  1113. clock-names = "bam_clk";
  1114. #dma-cells = <1>;
  1115. qcom,ee = <0>;
  1116. };
  1117. amba {
  1118. compatible = "arm,amba-bus";
  1119. #address-cells = <1>;
  1120. #size-cells = <1>;
  1121. ranges;
  1122. sdcc1: sdcc@12400000 {
  1123. status = "disabled";
  1124. compatible = "arm,pl18x", "arm,primecell";
  1125. arm,primecell-periphid = <0x00051180>;
  1126. reg = <0x12400000 0x2000>;
  1127. interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
  1128. interrupt-names = "cmd_irq";
  1129. clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
  1130. clock-names = "mclk", "apb_pclk";
  1131. bus-width = <8>;
  1132. max-frequency = <96000000>;
  1133. non-removable;
  1134. cap-sd-highspeed;
  1135. cap-mmc-highspeed;
  1136. vmmc-supply = <&vsdcc_fixed>;
  1137. dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
  1138. dma-names = "tx", "rx";
  1139. };
  1140. sdcc3: sdcc@12180000 {
  1141. compatible = "arm,pl18x", "arm,primecell";
  1142. arm,primecell-periphid = <0x00051180>;
  1143. status = "disabled";
  1144. reg = <0x12180000 0x2000>;
  1145. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  1146. interrupt-names = "cmd_irq";
  1147. clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
  1148. clock-names = "mclk", "apb_pclk";
  1149. bus-width = <8>;
  1150. cap-sd-highspeed;
  1151. cap-mmc-highspeed;
  1152. max-frequency = <192000000>;
  1153. #mmc-ddr-1_8v;
  1154. sd-uhs-sdr104;
  1155. sd-uhs-ddr50;
  1156. vqmmc-supply = <&vsdcc_fixed>;
  1157. dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
  1158. dma-names = "tx", "rx";
  1159. };
  1160. };
  1161. };
  1162. sfpb_mutex: sfpb-mutex {
  1163. compatible = "qcom,sfpb-mutex";
  1164. syscon = <&sfpb_mutex_block 4 4>;
  1165. #hwlock-cells = <1>;
  1166. };
  1167. smem {
  1168. compatible = "qcom,smem";
  1169. memory-region = <&smem>;
  1170. hwlocks = <&sfpb_mutex 3>;
  1171. };
  1172. };