qcom-ipq4018-jalapeno.dtsi 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. // Copyright (c) 2018, Robert Marko <[email protected]>
  3. #include "qcom-ipq4019.dtsi"
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. aliases {
  9. ethernet1 = &swport5;
  10. };
  11. soc {
  12. rng@22000 {
  13. status = "okay";
  14. };
  15. mdio@90000 {
  16. status = "okay";
  17. pinctrl-0 = <&mdio_pins>;
  18. pinctrl-names = "default";
  19. };
  20. counter@4a1000 {
  21. compatible = "qcom,qca-gcnt";
  22. reg = <0x4a1000 0x4>;
  23. };
  24. tcsr@1949000 {
  25. compatible = "qcom,tcsr";
  26. reg = <0x1949000 0x100>;
  27. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  28. };
  29. tcsr@194b000 {
  30. status = "okay";
  31. compatible = "qcom,tcsr";
  32. reg = <0x194b000 0x100>;
  33. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  34. };
  35. ess_tcsr@1953000 {
  36. compatible = "qcom,tcsr";
  37. reg = <0x1953000 0x1000>;
  38. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  39. };
  40. tcsr@1957000 {
  41. compatible = "qcom,tcsr";
  42. reg = <0x1957000 0x100>;
  43. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  44. };
  45. usb2: usb2@60f8800 {
  46. status = "okay";
  47. };
  48. usb3: usb3@8af8800 {
  49. status = "okay";
  50. };
  51. crypto@8e3a000 {
  52. status = "okay";
  53. };
  54. watchdog@b017000 {
  55. status = "okay";
  56. };
  57. };
  58. };
  59. &tlmm {
  60. mdio_pins: mdio_pinmux {
  61. pinmux_1 {
  62. pins = "gpio53";
  63. function = "mdio";
  64. };
  65. pinmux_2 {
  66. pins = "gpio52";
  67. function = "mdc";
  68. };
  69. pinconf {
  70. pins = "gpio52", "gpio53";
  71. bias-pull-up;
  72. };
  73. };
  74. serial_pins: serial_pinmux {
  75. mux {
  76. pins = "gpio60", "gpio61";
  77. function = "blsp_uart0";
  78. bias-disable;
  79. };
  80. };
  81. spi_0_pins: spi_0_pinmux {
  82. pin {
  83. function = "blsp_spi0";
  84. pins = "gpio55", "gpio56", "gpio57";
  85. drive-strength = <2>;
  86. bias-disable;
  87. };
  88. pin_cs {
  89. function = "gpio";
  90. pins = "gpio54", "gpio59";
  91. drive-strength = <2>;
  92. bias-disable;
  93. output-high;
  94. };
  95. };
  96. };
  97. &blsp_dma {
  98. status = "okay";
  99. };
  100. &blsp1_spi1 {
  101. status = "okay";
  102. pinctrl-0 = <&spi_0_pins>;
  103. pinctrl-names = "default";
  104. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
  105. flash@0 {
  106. status = "okay";
  107. compatible = "jedec,spi-nor";
  108. reg = <0>;
  109. spi-max-frequency = <24000000>;
  110. partitions {
  111. compatible = "fixed-partitions";
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. partition@0 {
  115. label = "SBL1";
  116. reg = <0x00000000 0x00040000>;
  117. read-only;
  118. };
  119. partition@40000 {
  120. label = "MIBIB";
  121. reg = <0x00040000 0x00020000>;
  122. read-only;
  123. };
  124. partition@60000 {
  125. label = "QSEE";
  126. reg = <0x00060000 0x00060000>;
  127. read-only;
  128. };
  129. partition@c0000 {
  130. label = "CDT";
  131. reg = <0x000c0000 0x00010000>;
  132. read-only;
  133. };
  134. partition@d0000 {
  135. label = "DDRPARAMS";
  136. reg = <0x000d0000 0x00010000>;
  137. read-only;
  138. };
  139. partition@e0000 {
  140. label = "APPSBLENV"; /* uboot env*/
  141. reg = <0x000e0000 0x00010000>;
  142. read-only;
  143. };
  144. partition@f0000 {
  145. label = "APPSBL"; /* uboot */
  146. reg = <0x000f0000 0x00080000>;
  147. read-only;
  148. };
  149. partition@170000 {
  150. label = "ART";
  151. reg = <0x00170000 0x00010000>;
  152. read-only;
  153. nvmem-layout {
  154. compatible = "fixed-layout";
  155. #address-cells = <1>;
  156. #size-cells = <1>;
  157. precal_art_1000: precal@1000 {
  158. reg = <0x1000 0x2f20>;
  159. };
  160. precal_art_5000: precal@5000 {
  161. reg = <0x5000 0x2f20>;
  162. };
  163. };
  164. };
  165. };
  166. };
  167. spi-nand@1 {
  168. status = "okay";
  169. compatible = "spi-nand";
  170. reg = <1>;
  171. spi-max-frequency = <24000000>;
  172. partitions {
  173. compatible = "fixed-partitions";
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. partition@0 {
  177. label = "ubi";
  178. reg = <0x00000000 0x08000000>;
  179. };
  180. };
  181. };
  182. };
  183. &blsp1_uart1 {
  184. status = "okay";
  185. pinctrl-0 = <&serial_pins>;
  186. pinctrl-names = "default";
  187. };
  188. &cryptobam {
  189. status = "okay";
  190. };
  191. &gmac {
  192. status = "okay";
  193. };
  194. &switch {
  195. status = "okay";
  196. };
  197. &swport4 {
  198. status = "okay";
  199. label = "lan";
  200. };
  201. &swport5 {
  202. status = "okay";
  203. };
  204. &wifi0 {
  205. status = "okay";
  206. nvmem-cell-names = "pre-calibration";
  207. nvmem-cells = <&precal_art_1000>;
  208. qcom,ath10k-calibration-variant = "8devices-Jalapeno";
  209. };
  210. &wifi1 {
  211. status = "okay";
  212. nvmem-cell-names = "pre-calibration";
  213. nvmem-cells = <&precal_art_5000>;
  214. qcom,ath10k-calibration-variant = "8devices-Jalapeno";
  215. };
  216. &usb3_ss_phy {
  217. status = "okay";
  218. };
  219. &usb3_hs_phy {
  220. status = "okay";
  221. };
  222. &usb2_hs_phy {
  223. status = "okay";
  224. };