| 12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091 |
- // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- #include "qcom-ipq4019-u4019.dtsi"
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/input/input.h>
- / {
- model = "Unielec U4019 (32M)";
- compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
- };
- &blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
- };
|
