815-v6.4-01-net-dsa-qca8k-move-qca8k_port_to_phy-to-header.patch 2.0 KB

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  1. From 3e8b4d6277fd19d98c817576954dd6a4ff3caa2b Mon Sep 17 00:00:00 2001
  2. From: Christian Marangi <[email protected]>
  3. Date: Mon, 17 Apr 2023 17:17:23 +0200
  4. Subject: [PATCH 1/9] net: dsa: qca8k: move qca8k_port_to_phy() to header
  5. Move qca8k_port_to_phy() to qca8k header as it's useful for future
  6. reference in Switch LEDs module since the same logic is applied to get
  7. the right index of the switch port.
  8. Make it inline as it's simple function that just decrease the port.
  9. Signed-off-by: Christian Marangi <[email protected]>
  10. Reviewed-by: Andrew Lunn <[email protected]>
  11. Reviewed-by: Michal Kubiak <[email protected]>
  12. Reviewed-by: Florian Fainelli <[email protected]>
  13. Signed-off-by: David S. Miller <[email protected]>
  14. ---
  15. drivers/net/dsa/qca/qca8k-8xxx.c | 15 ---------------
  16. drivers/net/dsa/qca/qca8k.h | 14 ++++++++++++++
  17. 2 files changed, 14 insertions(+), 15 deletions(-)
  18. --- a/drivers/net/dsa/qca/qca8k-8xxx.c
  19. +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
  20. @@ -716,21 +716,6 @@ err_clear_skb:
  21. return ret;
  22. }
  23. -static u32
  24. -qca8k_port_to_phy(int port)
  25. -{
  26. - /* From Andrew Lunn:
  27. - * Port 0 has no internal phy.
  28. - * Port 1 has an internal PHY at MDIO address 0.
  29. - * Port 2 has an internal PHY at MDIO address 1.
  30. - * ...
  31. - * Port 5 has an internal PHY at MDIO address 4.
  32. - * Port 6 has no internal PHY.
  33. - */
  34. -
  35. - return port - 1;
  36. -}
  37. -
  38. static int
  39. qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
  40. {
  41. --- a/drivers/net/dsa/qca/qca8k.h
  42. +++ b/drivers/net/dsa/qca/qca8k.h
  43. @@ -414,6 +414,20 @@ struct qca8k_fdb {
  44. u8 mac[6];
  45. };
  46. +static inline u32 qca8k_port_to_phy(int port)
  47. +{
  48. + /* From Andrew Lunn:
  49. + * Port 0 has no internal phy.
  50. + * Port 1 has an internal PHY at MDIO address 0.
  51. + * Port 2 has an internal PHY at MDIO address 1.
  52. + * ...
  53. + * Port 5 has an internal PHY at MDIO address 4.
  54. + * Port 6 has no internal PHY.
  55. + */
  56. +
  57. + return port - 1;
  58. +}
  59. +
  60. /* Common setup function */
  61. extern const struct qca8k_mib_desc ar8327_mib[];
  62. extern const struct regmap_access_table qca8k_readable_table;