MT7620a.dts 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130
  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  7. model = "Ralink MT7620a + MT7610e evaluation board";
  8. keys {
  9. compatible = "gpio-keys";
  10. poll-interval = <20>;
  11. s2 {
  12. label = "S2";
  13. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  14. linux,code = <BTN_0>;
  15. };
  16. s3 {
  17. label = "S3";
  18. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  19. linux,code = <BTN_1>;
  20. };
  21. };
  22. };
  23. &spi0 {
  24. status = "okay";
  25. m25p80@0 {
  26. compatible = "jedec,spi-nor";
  27. reg = <0>;
  28. spi-max-frequency = <10000000>;
  29. partitions {
  30. compatible = "fixed-partitions";
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. partition@0 {
  34. label = "u-boot";
  35. reg = <0x0 0x30000>;
  36. read-only;
  37. };
  38. partition@30000 {
  39. label = "u-boot-env";
  40. reg = <0x30000 0x10000>;
  41. read-only;
  42. };
  43. factory: partition@40000 {
  44. label = "factory";
  45. reg = <0x40000 0x10000>;
  46. read-only;
  47. };
  48. partition@50000 {
  49. compatible = "denx,uimage";
  50. label = "firmware";
  51. reg = <0x50000 0x7b0000>;
  52. };
  53. };
  54. };
  55. };
  56. &pinctrl {
  57. state_default: pinctrl0 {
  58. gpio {
  59. ralink,group = "i2c", "uartf";
  60. ralink,function = "gpio";
  61. };
  62. };
  63. };
  64. &ethernet {
  65. status = "okay";
  66. pinctrl-names = "default";
  67. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  68. mediatek,portmap = "llllw";
  69. port@4 {
  70. status = "okay";
  71. phy-mode = "rgmii";
  72. phy-handle = <&phy4>;
  73. };
  74. port@5 {
  75. status = "okay";
  76. phy-mode = "rgmii";
  77. phy-handle = <&phy5>;
  78. };
  79. mdio-bus {
  80. status = "okay";
  81. phy4: ethernet-phy@4 {
  82. reg = <4>;
  83. phy-mode = "rgmii";
  84. };
  85. phy5: ethernet-phy@5 {
  86. reg = <5>;
  87. phy-mode = "rgmii";
  88. };
  89. };
  90. };
  91. &gsw {
  92. mediatek,port4 = "gmac";
  93. };
  94. &sdhci {
  95. status = "okay";
  96. };
  97. &pcie {
  98. status = "okay";
  99. };
  100. &ehci {
  101. status = "okay";
  102. };
  103. &ohci {
  104. status = "okay";
  105. };