cn9131-puzzle-m901.dts 7.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
  2. /*
  3. * Copyright (C) 2019 Marvell International Ltd.
  4. *
  5. * Device tree for the CN9131-DB board.
  6. */
  7. #include "cn9130.dtsi"
  8. #include "puzzle-thermal.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. #include <dt-bindings/leds/common.h>
  12. / {
  13. model = "iEi Puzzle-M901";
  14. compatible = "iei,puzzle-m901",
  15. "marvell,armada-ap807-quad", "marvell,armada-ap807";
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. aliases {
  20. i2c0 = &cp1_i2c0;
  21. i2c1 = &cp0_i2c0;
  22. ethernet0 = &cp0_eth0;
  23. ethernet1 = &cp0_eth1;
  24. ethernet2 = &cp0_eth2;
  25. ethernet3 = &cp1_eth0;
  26. ethernet4 = &cp1_eth1;
  27. ethernet5 = &cp1_eth2;
  28. gpio1 = &cp0_gpio1;
  29. gpio2 = &cp0_gpio2;
  30. gpio3 = &cp1_gpio1;
  31. gpio4 = &cp1_gpio2;
  32. led-boot = &led_power;
  33. led-failsafe = &led_info;
  34. led-running = &led_power;
  35. led-upgrade = &led_info;
  36. };
  37. memory@00000000 {
  38. device_type = "memory";
  39. reg = <0x0 0x0 0x0 0x80000000>;
  40. };
  41. gpio_keys {
  42. compatible = "gpio-keys";
  43. reset {
  44. label = "Reset";
  45. linux,code = <KEY_RESTART>;
  46. gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  47. };
  48. };
  49. };
  50. &uart0 {
  51. status = "okay";
  52. };
  53. &cp0_uart0 {
  54. status = "okay";
  55. puzzle-mcu {
  56. compatible = "iei,wt61p803-puzzle";
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. current-speed = <115200>;
  60. enable-beep;
  61. status = "okay";
  62. leds {
  63. compatible = "iei,wt61p803-puzzle-leds";
  64. #address-cells = <1>;
  65. #size-cells = <0>;
  66. status = "okay";
  67. led@0 {
  68. reg = <0>;
  69. label = "white:network";
  70. active-low;
  71. };
  72. led@1 {
  73. reg = <1>;
  74. label = "green:cloud";
  75. active-low;
  76. };
  77. led_info: led@2 {
  78. reg = <2>;
  79. label = "orange:info";
  80. active-low;
  81. };
  82. led_power: led@3 {
  83. reg = <3>;
  84. function = LED_FUNCTION_POWER;
  85. color = <LED_COLOR_ID_YELLOW>;
  86. active-low;
  87. default-state = "on";
  88. };
  89. };
  90. hwmon {
  91. compatible = "iei,wt61p803-puzzle-hwmon";
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. chassis_fan_group0: fan-group@0 {
  95. #cooling-cells = <2>;
  96. reg = <0x00>;
  97. cooling-levels = <80 102 170 230 255>;
  98. };
  99. };
  100. };
  101. };
  102. &ap_thermal_ic {
  103. PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
  104. };
  105. &cp0_thermal_ic {
  106. PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
  107. };
  108. /* on-board eMMC - U9 */
  109. &ap_sdhci0 {
  110. pinctrl-names = "default";
  111. bus-width = <8>;
  112. status = "okay";
  113. mmc-ddr-1_8v;
  114. mmc-hs400-1_8v;
  115. };
  116. &cp0_crypto {
  117. status = "okay";
  118. };
  119. &cp0_xmdio {
  120. status = "okay";
  121. cp0_nbaset_phy0: ethernet-phy@0 {
  122. compatible = "ethernet-phy-ieee802.3-c45";
  123. reg = <2>;
  124. };
  125. cp0_nbaset_phy1: ethernet-phy@1 {
  126. compatible = "ethernet-phy-ieee802.3-c45";
  127. reg = <0>;
  128. };
  129. cp0_nbaset_phy2: ethernet-phy@2 {
  130. compatible = "ethernet-phy-ieee802.3-c45";
  131. reg = <8>;
  132. };
  133. };
  134. &cp0_ethernet {
  135. status = "okay";
  136. };
  137. /* SLM-1521-V2, CON9 */
  138. &cp0_eth0 {
  139. status = "okay";
  140. phy-mode = "2500base-x";
  141. phys = <&cp0_comphy2 0>;
  142. phy = <&cp0_nbaset_phy0>;
  143. };
  144. &cp0_eth1 {
  145. status = "okay";
  146. phy-mode = "2500base-x";
  147. phys = <&cp0_comphy4 1>;
  148. phy = <&cp0_nbaset_phy1>;
  149. };
  150. &cp0_eth2 {
  151. status = "okay";
  152. phy-mode = "2500base-x";
  153. phys = <&cp0_comphy5 2>;
  154. phy = <&cp0_nbaset_phy2>;
  155. };
  156. &cp0_gpio1 {
  157. status = "okay";
  158. };
  159. &cp0_gpio2 {
  160. status = "okay";
  161. };
  162. &cp0_i2c0 {
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&cp0_i2c0_pins>;
  165. status = "okay";
  166. clock-frequency = <100000>;
  167. rtc@32 {
  168. compatible = "epson,rx8130";
  169. reg = <0x32>;
  170. wakeup-source;
  171. };
  172. };
  173. /* SLM-1521-V2, CON6 */
  174. &cp0_pcie0 {
  175. status = "okay";
  176. num-lanes = <2>;
  177. num-viewport = <8>;
  178. phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
  179. };
  180. /* U55 */
  181. &cp0_spi1 {
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&cp0_spi0_pins>;
  184. reg = <0x700680 0x50>, /* control */
  185. <0x2000000 0x1000000>; /* CS0 */
  186. status = "okay";
  187. spi-flash@0 {
  188. #address-cells = <0x1>;
  189. #size-cells = <0x1>;
  190. compatible = "jedec,spi-nor";
  191. reg = <0x0>;
  192. spi-max-frequency = <40000000>;
  193. partitions {
  194. compatible = "fixed-partitions";
  195. #address-cells = <1>;
  196. #size-cells = <1>;
  197. partition@0 {
  198. label = "U-Boot";
  199. reg = <0x0 0x1f0000>;
  200. };
  201. partition@1f0000 {
  202. label = "U-Boot ENV Factory";
  203. reg = <0x1f0000 0x10000>;
  204. };
  205. partition@200000 {
  206. label = "Reserved";
  207. reg = <0x200000 0x1f0000>;
  208. };
  209. partition@3f0000 {
  210. label = "U-Boot ENV";
  211. reg = <0x3f0000 0x10000>;
  212. };
  213. };
  214. };
  215. };
  216. &cp0_rtc {
  217. status = "disabled";
  218. };
  219. &cp0_syscon0 {
  220. cp0_pinctrl: pinctrl {
  221. compatible = "marvell,cp115-standalone-pinctrl";
  222. cp0_i2c0_pins: cp0-i2c-pins-0 {
  223. marvell,pins = "mpp37", "mpp38";
  224. marvell,function = "i2c0";
  225. };
  226. cp0_i2c1_pins: cp0-i2c-pins-1 {
  227. marvell,pins = "mpp35", "mpp36";
  228. marvell,function = "i2c1";
  229. };
  230. cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
  231. marvell,pins = "mpp0", "mpp1", "mpp2",
  232. "mpp3", "mpp4", "mpp5",
  233. "mpp6", "mpp7", "mpp8",
  234. "mpp9", "mpp10", "mpp11";
  235. marvell,function = "ge0";
  236. };
  237. cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
  238. marvell,pins = "mpp44", "mpp45", "mpp46",
  239. "mpp47", "mpp48", "mpp49",
  240. "mpp50", "mpp51", "mpp52",
  241. "mpp53", "mpp54", "mpp55";
  242. marvell,function = "ge1";
  243. };
  244. cp0_spi0_pins: cp0-spi-pins-0 {
  245. marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
  246. marvell,function = "spi1";
  247. };
  248. };
  249. };
  250. /*
  251. * Instantiate the first connected CP115
  252. */
  253. #define CP11X_NAME cp1
  254. #define CP11X_BASE f6000000
  255. #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
  256. #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
  257. #define CP11X_PCIE0_BASE f6600000
  258. #define CP11X_PCIE1_BASE f6620000
  259. #define CP11X_PCIE2_BASE f6640000
  260. #include "armada-cp115.dtsi"
  261. #undef CP11X_NAME
  262. #undef CP11X_BASE
  263. #undef CP11X_PCIEx_MEM_BASE
  264. #undef CP11X_PCIEx_MEM_SIZE
  265. #undef CP11X_PCIE0_BASE
  266. #undef CP11X_PCIE1_BASE
  267. #undef CP11X_PCIE2_BASE
  268. &cp1_crypto {
  269. status = "okay";
  270. };
  271. &cp1_xmdio {
  272. status = "okay";
  273. cp1_nbaset_phy0: ethernet-phy@3 {
  274. compatible = "ethernet-phy-ieee802.3-c45";
  275. reg = <2>;
  276. };
  277. cp1_nbaset_phy1: ethernet-phy@4 {
  278. compatible = "ethernet-phy-ieee802.3-c45";
  279. reg = <0>;
  280. };
  281. cp1_nbaset_phy2: ethernet-phy@5 {
  282. compatible = "ethernet-phy-ieee802.3-c45";
  283. reg = <8>;
  284. };
  285. };
  286. &cp1_ethernet {
  287. status = "okay";
  288. };
  289. /* CON50 */
  290. &cp1_eth0 {
  291. status = "okay";
  292. phy-mode = "2500base-x";
  293. phys = <&cp1_comphy2 0>;
  294. phy = <&cp1_nbaset_phy0>;
  295. };
  296. &cp1_eth1 {
  297. status = "okay";
  298. phy-mode = "2500base-x";
  299. phys = <&cp1_comphy4 1>;
  300. phy = <&cp1_nbaset_phy1>;
  301. };
  302. &cp1_eth2 {
  303. status = "okay";
  304. phy-mode = "2500base-x";
  305. phys = <&cp1_comphy5 2>;
  306. phy = <&cp1_nbaset_phy2>;
  307. };
  308. &cp1_sata0 {
  309. status = "okay";
  310. sata-port@1 {
  311. status = "okay";
  312. phys = <&cp1_comphy0 1>;
  313. };
  314. };
  315. &cp1_gpio1 {
  316. status = "okay";
  317. };
  318. &cp1_gpio2 {
  319. status = "okay";
  320. };
  321. &cp1_i2c0 {
  322. status = "okay";
  323. pinctrl-names = "default";
  324. pinctrl-0 = <&cp1_i2c0_pins>;
  325. clock-frequency = <100000>;
  326. };
  327. &cp1_rtc {
  328. status = "disabled";
  329. };
  330. &cp1_syscon0 {
  331. cp1_pinctrl: pinctrl {
  332. compatible = "marvell,cp115-standalone-pinctrl";
  333. cp1_i2c0_pins: cp1-i2c-pins-0 {
  334. marvell,pins = "mpp37", "mpp38";
  335. marvell,function = "i2c0";
  336. };
  337. cp1_spi0_pins: cp1-spi-pins-0 {
  338. marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
  339. marvell,function = "spi1";
  340. };
  341. cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
  342. marvell,pins = "mpp3";
  343. marvell,function = "gpio";
  344. };
  345. cp1_sfp_pins: sfp-pins {
  346. marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
  347. marvell,function = "gpio";
  348. };
  349. };
  350. };
  351. &cp1_thermal_ic {
  352. PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
  353. };
  354. &cp1_usb3_1 {
  355. status = "okay";
  356. phys = <&cp1_comphy3 1>;
  357. phy-names = "usb";
  358. };