cn9132-puzzle-m902.dts 11 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
  2. /*
  3. * Copyright (C) 2019 Marvell International Ltd.
  4. *
  5. * Device tree for the CN9132-DB board.
  6. */
  7. #include "cn9130.dtsi"
  8. #include "puzzle-thermal.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. #include <dt-bindings/leds/common.h>
  12. / {
  13. model = "iEi Puzzle-M902";
  14. compatible = "iei,puzzle-m902",
  15. "marvell,armada-ap807-quad", "marvell,armada-ap807";
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. aliases {
  20. i2c0 = &cp1_i2c0;
  21. i2c1 = &cp0_i2c0;
  22. gpio1 = &cp0_gpio1;
  23. gpio2 = &cp0_gpio2;
  24. gpio3 = &cp1_gpio1;
  25. gpio4 = &cp1_gpio2;
  26. gpio5 = &cp2_gpio1;
  27. gpio6 = &cp2_gpio2;
  28. ethernet0 = &cp0_eth0;
  29. ethernet1 = &cp0_eth1;
  30. ethernet2 = &cp0_eth2;
  31. ethernet3 = &cp1_eth0;
  32. ethernet4 = &cp1_eth1;
  33. ethernet5 = &cp1_eth2;
  34. ethernet6 = &cp2_eth0;
  35. ethernet7 = &cp2_eth1;
  36. ethernet8 = &cp2_eth2;
  37. spi1 = &cp0_spi0;
  38. spi2 = &cp0_spi1;
  39. led-boot = &led_power;
  40. led-failsafe = &led_info;
  41. led-running = &led_power;
  42. led-upgrade = &led_info;
  43. };
  44. memory@00000000 {
  45. device_type = "memory";
  46. reg = <0x0 0x0 0x0 0x80000000>;
  47. };
  48. gpio_keys {
  49. compatible = "gpio-keys";
  50. reset {
  51. label = "Reset";
  52. linux,code = <KEY_RESTART>;
  53. gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  54. };
  55. };
  56. cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
  57. compatible = "regulator-fixed";
  58. regulator-name = "cp2-xhci0-vbus";
  59. regulator-min-microvolt = <5000000>;
  60. regulator-max-microvolt = <5000000>;
  61. enable-active-high;
  62. gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
  63. };
  64. cp2_usb3_0_phy0: cp2_usb3_phy0 {
  65. compatible = "usb-nop-xceiv";
  66. vcc-supply = <&cp2_reg_usb3_vbus0>;
  67. };
  68. cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
  69. compatible = "regulator-fixed";
  70. regulator-name = "cp2-xhci1-vbus";
  71. regulator-min-microvolt = <5000000>;
  72. regulator-max-microvolt = <5000000>;
  73. enable-active-high;
  74. gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
  75. };
  76. cp2_usb3_0_phy1: cp2_usb3_phy1 {
  77. compatible = "usb-nop-xceiv";
  78. vcc-supply = <&cp2_reg_usb3_vbus1>;
  79. };
  80. cp2_sfp_eth0: sfp-eth0 {
  81. compatible = "sff,sfp";
  82. i2c-bus = <&cp2_sfpp0_i2c>;
  83. los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
  84. mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
  85. tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
  86. tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
  87. status = "disabled";
  88. };
  89. };
  90. &uart0 {
  91. status = "okay";
  92. };
  93. &cp0_uart0 {
  94. status = "okay";
  95. puzzle-mcu {
  96. compatible = "iei,wt61p803-puzzle";
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. current-speed = <115200>;
  100. enable-beep;
  101. status = "okay";
  102. leds {
  103. compatible = "iei,wt61p803-puzzle-leds";
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. status = "okay";
  107. led@0 {
  108. reg = <0>;
  109. label = "white:network";
  110. active-low;
  111. };
  112. led@1 {
  113. reg = <1>;
  114. label = "green:cloud";
  115. active-low;
  116. };
  117. led_info: led@2 {
  118. reg = <2>;
  119. label = "orange:info";
  120. active-low;
  121. };
  122. led_power: led@3 {
  123. reg = <3>;
  124. function = LED_FUNCTION_POWER;
  125. color = <LED_COLOR_ID_YELLOW>;
  126. active-low;
  127. default-state = "on";
  128. };
  129. };
  130. hwmon {
  131. compatible = "iei,wt61p803-puzzle-hwmon";
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. chassis_fan_group0: fan-group@0 {
  135. #cooling-cells = <2>;
  136. reg = <0x00>;
  137. cooling-levels = <80 102 170 230 255>;
  138. };
  139. };
  140. };
  141. };
  142. &ap_thermal_ic {
  143. PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
  144. };
  145. &cp0_thermal_ic {
  146. PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
  147. };
  148. /* on-board eMMC - U9 */
  149. &ap_sdhci0 {
  150. pinctrl-names = "default";
  151. bus-width = <8>;
  152. status = "okay";
  153. mmc-ddr-1_8v;
  154. mmc-hs400-1_8v;
  155. };
  156. &cp0_crypto {
  157. status = "okay";
  158. };
  159. &cp0_xmdio {
  160. status = "okay";
  161. cp0_nbaset_phy0: ethernet-phy@0 {
  162. compatible = "ethernet-phy-ieee802.3-c45";
  163. reg = <2>;
  164. };
  165. cp0_nbaset_phy1: ethernet-phy@1 {
  166. compatible = "ethernet-phy-ieee802.3-c45";
  167. reg = <0>;
  168. };
  169. cp0_nbaset_phy2: ethernet-phy@2 {
  170. compatible = "ethernet-phy-ieee802.3-c45";
  171. reg = <8>;
  172. };
  173. };
  174. &cp0_ethernet {
  175. status = "okay";
  176. };
  177. /* SLM-1521-V2, CON9 */
  178. &cp0_eth0 {
  179. status = "okay";
  180. phy-mode = "10gbase-kr";
  181. phys = <&cp0_comphy2 0>;
  182. phy = <&cp0_nbaset_phy0>;
  183. };
  184. &cp0_eth1 {
  185. status = "okay";
  186. phy-mode = "2500base-x";
  187. phys = <&cp0_comphy4 1>;
  188. phy = <&cp0_nbaset_phy1>;
  189. };
  190. &cp0_eth2 {
  191. status = "okay";
  192. phy-mode = "2500base-x";
  193. phys = <&cp0_comphy1 2>;
  194. phy = <&cp0_nbaset_phy2>;
  195. };
  196. &cp0_gpio1 {
  197. status = "okay";
  198. };
  199. &cp0_gpio2 {
  200. status = "okay";
  201. };
  202. &cp0_i2c0 {
  203. pinctrl-names = "default";
  204. pinctrl-0 = <&cp0_i2c0_pins>;
  205. status = "okay";
  206. clock-frequency = <100000>;
  207. rtc@32 {
  208. compatible = "epson,rx8130";
  209. reg = <0x32>;
  210. wakeup-source;
  211. };
  212. };
  213. &cp0_i2c1 {
  214. clock-frequency = <100000>;
  215. };
  216. /* SLM-1521-V2, CON6 */
  217. &cp0_sata0 {
  218. status = "okay";
  219. sata-port@1 {
  220. status = "okay";
  221. phys = <&cp0_comphy0 1>;
  222. };
  223. };
  224. &cp0_pcie2 {
  225. status = "okay";
  226. num-lanes = <1>;
  227. num-viewport = <8>;
  228. phys = <&cp0_comphy5 2>;
  229. };
  230. /* U55 */
  231. &cp0_spi1 {
  232. pinctrl-names = "default";
  233. pinctrl-0 = <&cp0_spi0_pins>;
  234. reg = <0x700680 0x50>, /* control */
  235. <0x2000000 0x1000000>; /* CS0 */
  236. status = "okay";
  237. spi-flash@0 {
  238. #address-cells = <0x1>;
  239. #size-cells = <0x1>;
  240. compatible = "jedec,spi-nor";
  241. reg = <0x0>;
  242. spi-max-frequency = <40000000>;
  243. partitions {
  244. compatible = "fixed-partitions";
  245. #address-cells = <1>;
  246. #size-cells = <1>;
  247. partition@0 {
  248. label = "U-Boot";
  249. reg = <0x0 0x1f0000>;
  250. };
  251. partition@1f0000 {
  252. label = "U-Boot ENV Factory";
  253. reg = <0x1f0000 0x10000>;
  254. };
  255. partition@200000 {
  256. label = "Reserved";
  257. reg = <0x200000 0x1f0000>;
  258. };
  259. partition@3f0000 {
  260. label = "U-Boot ENV";
  261. reg = <0x3f0000 0x10000>;
  262. };
  263. };
  264. };
  265. };
  266. &cp0_rtc {
  267. status = "disabled";
  268. };
  269. &cp0_syscon0 {
  270. cp0_pinctrl: pinctrl {
  271. compatible = "marvell,cp115-standalone-pinctrl";
  272. cp0_i2c0_pins: cp0-i2c-pins-0 {
  273. marvell,pins = "mpp37", "mpp38";
  274. marvell,function = "i2c0";
  275. };
  276. cp0_i2c1_pins: cp0-i2c-pins-1 {
  277. marvell,pins = "mpp35", "mpp36";
  278. marvell,function = "i2c1";
  279. };
  280. cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
  281. marvell,pins = "mpp0", "mpp1", "mpp2",
  282. "mpp3", "mpp4", "mpp5",
  283. "mpp6", "mpp7", "mpp8",
  284. "mpp9", "mpp10", "mpp11";
  285. marvell,function = "ge0";
  286. };
  287. cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
  288. marvell,pins = "mpp44", "mpp45", "mpp46",
  289. "mpp47", "mpp48", "mpp49",
  290. "mpp50", "mpp51", "mpp52",
  291. "mpp53", "mpp54", "mpp55";
  292. marvell,function = "ge1";
  293. };
  294. cp0_spi0_pins: cp0-spi-pins-0 {
  295. marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
  296. marvell,function = "spi1";
  297. };
  298. };
  299. };
  300. &cp0_usb3_1 {
  301. status = "okay";
  302. phys = <&cp0_comphy3 1>;
  303. phy-names = "usb";
  304. };
  305. /*
  306. * Instantiate the first connected CP115
  307. */
  308. #define CP11X_NAME cp1
  309. #define CP11X_BASE f4000000
  310. #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
  311. #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
  312. #define CP11X_PCIE0_BASE f4600000
  313. #define CP11X_PCIE1_BASE f4620000
  314. #define CP11X_PCIE2_BASE f4640000
  315. #include "armada-cp115.dtsi"
  316. #undef CP11X_NAME
  317. #undef CP11X_BASE
  318. #undef CP11X_PCIEx_MEM_BASE
  319. #undef CP11X_PCIEx_MEM_SIZE
  320. #undef CP11X_PCIE0_BASE
  321. #undef CP11X_PCIE1_BASE
  322. #undef CP11X_PCIE2_BASE
  323. &cp1_crypto {
  324. status = "okay";
  325. };
  326. &cp1_xmdio {
  327. status = "okay";
  328. cp1_nbaset_phy0: ethernet-phy@3 {
  329. compatible = "ethernet-phy-ieee802.3-c45";
  330. reg = <2>;
  331. };
  332. cp1_nbaset_phy1: ethernet-phy@4 {
  333. compatible = "ethernet-phy-ieee802.3-c45";
  334. reg = <0>;
  335. };
  336. cp1_nbaset_phy2: ethernet-phy@5 {
  337. compatible = "ethernet-phy-ieee802.3-c45";
  338. reg = <8>;
  339. };
  340. };
  341. &cp1_ethernet {
  342. status = "okay";
  343. };
  344. /* CON50 */
  345. &cp1_eth0 {
  346. status = "okay";
  347. phy-mode = "10gbase-kr";
  348. phys = <&cp1_comphy2 0>;
  349. phy = <&cp1_nbaset_phy0>;
  350. };
  351. &cp1_eth1 {
  352. status = "okay";
  353. phy-mode = "2500base-x";
  354. phys = <&cp1_comphy4 1>;
  355. phy = <&cp1_nbaset_phy1>;
  356. };
  357. &cp1_eth2 {
  358. status = "okay";
  359. phy-mode = "2500base-x";
  360. phys = <&cp1_comphy1 2>;
  361. phy = <&cp1_nbaset_phy2>;
  362. };
  363. &cp1_gpio1 {
  364. status = "okay";
  365. };
  366. &cp1_gpio2 {
  367. status = "okay";
  368. };
  369. &cp1_i2c0 {
  370. status = "okay";
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&cp1_i2c0_pins>;
  373. clock-frequency = <100000>;
  374. };
  375. &cp1_rtc {
  376. status = "disabled";
  377. };
  378. &cp1_syscon0 {
  379. cp1_pinctrl: pinctrl {
  380. compatible = "marvell,cp115-standalone-pinctrl";
  381. cp1_i2c0_pins: cp1-i2c-pins-0 {
  382. marvell,pins = "mpp37", "mpp38";
  383. marvell,function = "i2c0";
  384. };
  385. cp1_spi0_pins: cp1-spi-pins-0 {
  386. marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
  387. marvell,function = "spi1";
  388. };
  389. cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
  390. marvell,pins = "mpp3";
  391. marvell,function = "gpio";
  392. };
  393. };
  394. };
  395. &cp1_thermal_ic {
  396. PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
  397. };
  398. /*
  399. * Instantiate the second connected CP115
  400. */
  401. #define CP11X_NAME cp2
  402. #define CP11X_BASE f6000000
  403. #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
  404. #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
  405. #define CP11X_PCIE0_BASE f6600000
  406. #define CP11X_PCIE1_BASE f6620000
  407. #define CP11X_PCIE2_BASE f6640000
  408. #include "armada-cp115.dtsi"
  409. #undef CP11X_NAME
  410. #undef CP11X_BASE
  411. #undef CP11X_PCIEx_MEM_BASE
  412. #undef CP11X_PCIEx_MEM_SIZE
  413. #undef CP11X_PCIE0_BASE
  414. #undef CP11X_PCIE1_BASE
  415. #undef CP11X_PCIE2_BASE
  416. &cp2_crypto {
  417. status = "okay";
  418. };
  419. &cp2_ethernet {
  420. status = "okay";
  421. };
  422. &cp2_xmdio {
  423. status = "okay";
  424. cp2_nbaset_phy0: ethernet-phy@6 {
  425. compatible = "ethernet-phy-ieee802.3-c45";
  426. reg = <2>;
  427. };
  428. cp2_nbaset_phy1: ethernet-phy@7 {
  429. compatible = "ethernet-phy-ieee802.3-c45";
  430. reg = <0>;
  431. };
  432. cp2_nbaset_phy2: ethernet-phy@8 {
  433. compatible = "ethernet-phy-ieee802.3-c45";
  434. reg = <8>;
  435. };
  436. };
  437. /* SLM-1521-V2, CON9 */
  438. &cp2_eth0 {
  439. status = "okay";
  440. phy-mode = "10gbase-kr";
  441. phys = <&cp2_comphy2 0>;
  442. phy = <&cp2_nbaset_phy0>;
  443. };
  444. &cp2_eth1 {
  445. status = "okay";
  446. phy-mode = "2500base-x";
  447. phys = <&cp2_comphy4 1>;
  448. phy = <&cp2_nbaset_phy1>;
  449. };
  450. &cp2_eth2 {
  451. status = "okay";
  452. phy-mode = "2500base-x";
  453. phys = <&cp2_comphy1 2>;
  454. phy = <&cp2_nbaset_phy2>;
  455. };
  456. &cp2_gpio1 {
  457. status = "okay";
  458. };
  459. &cp2_gpio2 {
  460. status = "okay";
  461. };
  462. &cp2_i2c0 {
  463. clock-frequency = <100000>;
  464. /* SLM-1521-V2 - U3 */
  465. i2c-mux@72 {
  466. compatible = "nxp,pca9544";
  467. #address-cells = <1>;
  468. #size-cells = <0>;
  469. reg = <0x72>;
  470. cp2_sfpp0_i2c: i2c@0 {
  471. #address-cells = <1>;
  472. #size-cells = <0>;
  473. reg = <0>;
  474. };
  475. i2c@1 {
  476. #address-cells = <1>;
  477. #size-cells = <0>;
  478. reg = <1>;
  479. /* U12 */
  480. cp2_module_expander1: pca9555@21 {
  481. compatible = "nxp,pca9555";
  482. pinctrl-names = "default";
  483. gpio-controller;
  484. #gpio-cells = <2>;
  485. reg = <0x21>;
  486. };
  487. };
  488. };
  489. };
  490. &cp2_rtc {
  491. status = "disabled";
  492. };
  493. &cp2_syscon0 {
  494. cp2_pinctrl: pinctrl {
  495. compatible = "marvell,cp115-standalone-pinctrl";
  496. cp2_i2c0_pins: cp2-i2c-pins-0 {
  497. marvell,pins = "mpp37", "mpp38";
  498. marvell,function = "i2c0";
  499. };
  500. };
  501. };
  502. &cp2_thermal_ic {
  503. PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
  504. };