qcom-ipq4018-cs-w3-wd1200g-eup.dts 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "EZVIZ CS-W3-WD1200G EUP";
  8. compatible = "ezviz,cs-w3-wd1200g-eup";
  9. aliases {
  10. led-boot = &led_status_green;
  11. led-failsafe = &led_status_red;
  12. led-running = &led_status_blue;
  13. led-upgrade = &led_status_green;
  14. };
  15. soc {
  16. rng@22000 {
  17. status = "okay";
  18. };
  19. mdio@90000 {
  20. status = "okay";
  21. pinctrl-0 = <&mdio_pins>;
  22. pinctrl-names = "default";
  23. reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
  24. reset-delay-us = <5000>;
  25. };
  26. ess-psgmii@98000 {
  27. status = "okay";
  28. };
  29. tcsr@1949000 {
  30. compatible = "qcom,tcsr";
  31. reg = <0x1949000 0x100>;
  32. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  33. };
  34. tcsr@194b000 {
  35. compatible = "qcom,tcsr";
  36. reg = <0x194b000 0x100>;
  37. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  38. };
  39. ess_tcsr@1953000 {
  40. compatible = "qcom,tcsr";
  41. reg = <0x1953000 0x1000>;
  42. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  43. };
  44. tcsr@1957000 {
  45. compatible = "qcom,tcsr";
  46. reg = <0x1957000 0x100>;
  47. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  48. };
  49. crypto@8e3a000 {
  50. status = "okay";
  51. };
  52. watchdog@b017000 {
  53. status = "okay";
  54. };
  55. ess-switch@c000000 {
  56. status = "okay";
  57. };
  58. edma@c080000 {
  59. status = "okay";
  60. };
  61. };
  62. leds {
  63. compatible = "gpio-leds";
  64. led_status_red: status_red {
  65. label = "cs-w3-wd1200g-eup:red:status";
  66. gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  67. };
  68. led_status_green: status_green {
  69. label = "cs-w3-wd1200g-eup:green:status";
  70. gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
  71. };
  72. led_status_blue: status_blue {
  73. label = "cs-w3-wd1200g-eup:blue:status";
  74. gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
  75. };
  76. };
  77. keys {
  78. compatible = "gpio-keys";
  79. reset {
  80. label = "reset";
  81. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  82. linux,code = <KEY_RESTART>;
  83. };
  84. };
  85. };
  86. &tlmm {
  87. serial_pins: serial_pinmux {
  88. mux {
  89. pins = "gpio60", "gpio61";
  90. function = "blsp_uart0";
  91. bias-disable;
  92. };
  93. };
  94. mdio_pins: mdio_pinmux {
  95. mux_1 {
  96. pins = "gpio53";
  97. function = "mdio";
  98. bias-pull-up;
  99. };
  100. mux_2 {
  101. pins = "gpio52";
  102. function = "mdc";
  103. bias-pull-up;
  104. };
  105. };
  106. spi_0_pins: spi_0_pinmux {
  107. pin {
  108. function = "blsp_spi0";
  109. pins = "gpio55", "gpio56", "gpio57";
  110. drive-strength = <12>;
  111. bias-disable;
  112. };
  113. pin_cs {
  114. function = "gpio";
  115. pins = "gpio54";
  116. drive-strength = <2>;
  117. bias-disable;
  118. output-high;
  119. };
  120. };
  121. };
  122. &blsp_dma {
  123. status = "okay";
  124. };
  125. &blsp1_spi1 {
  126. pinctrl-0 = <&spi_0_pins>;
  127. pinctrl-names = "default";
  128. status = "okay";
  129. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
  130. flash@0 {
  131. compatible = "jedec,spi-nor";
  132. reg = <0>;
  133. spi-max-frequency = <24000000>;
  134. partitions {
  135. compatible = "fixed-partitions";
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. partition0@0 {
  139. label = "SBL1";
  140. reg = <0x00000000 0x00040000>;
  141. read-only;
  142. };
  143. partition1@40000 {
  144. label = "MIBIB";
  145. reg = <0x00040000 0x00020000>;
  146. read-only;
  147. };
  148. partition2@60000 {
  149. label = "QSEE";
  150. reg = <0x00060000 0x00060000>;
  151. read-only;
  152. };
  153. partition3@c0000 {
  154. label = "CDT";
  155. reg = <0x000c0000 0x00010000>;
  156. read-only;
  157. };
  158. partition4@d0000 {
  159. label = "DDRPARAMS";
  160. reg = <0x000d0000 0x00010000>;
  161. read-only;
  162. };
  163. partition5@E0000 {
  164. label = "APPSBLENV";
  165. reg = <0x000e0000 0x00010000>;
  166. read-only;
  167. };
  168. partition6@F0000 {
  169. label = "APPSBL";
  170. reg = <0x000f0000 0x00080000>;
  171. read-only;
  172. };
  173. partition7@170000 {
  174. label = "ART";
  175. reg = <0x00170000 0x00010000>;
  176. read-only;
  177. };
  178. partition9@580000 {
  179. compatible = "denx,fit";
  180. label = "firmware";
  181. reg = <0x00180000 0x00e80000>;
  182. };
  183. };
  184. };
  185. };
  186. &blsp1_uart1 {
  187. pinctrl-0 = <&serial_pins>;
  188. pinctrl-names = "default";
  189. status = "okay";
  190. };
  191. &cryptobam {
  192. status = "okay";
  193. };
  194. &wifi0 {
  195. status = "okay";
  196. qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
  197. };
  198. &wifi1 {
  199. status = "okay";
  200. qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
  201. };