0123-MIPS-ralink-add-memory-definition-for-RT305x.patch 2.5 KB

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  1. From 1a255c5e67baad1735f985ad818d2b970fcc6808 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Sat, 13 Apr 2013 15:13:40 +0200
  4. Subject: [PATCH 123/164] MIPS: ralink: add memory definition for RT305x
  5. Populate struct soc_info with the data that describes our RAM window.
  6. As memory detection fails on RT5350 we read the amount of available memory
  7. from the system controller.
  8. Signed-off-by: John Crispin <[email protected]>
  9. Patchwork: http://patchwork.linux-mips.org/patch/5180/
  10. ---
  11. arch/mips/include/asm/mach-ralink/rt305x.h | 6 ++++
  12. arch/mips/ralink/rt305x.c | 45 ++++++++++++++++++++++++++++
  13. 2 files changed, 51 insertions(+)
  14. --- a/arch/mips/include/asm/mach-ralink/rt305x.h
  15. +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
  16. @@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
  17. #define RT3352_RSTCTRL_UDEV BIT(25)
  18. #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
  19. +#define RT305X_SDRAM_BASE 0x00000000
  20. +#define RT305X_MEM_SIZE_MIN 2
  21. +#define RT305X_MEM_SIZE_MAX 64
  22. +#define RT3352_MEM_SIZE_MIN 2
  23. +#define RT3352_MEM_SIZE_MAX 256
  24. +
  25. #endif
  26. --- a/arch/mips/ralink/rt305x.c
  27. +++ b/arch/mips/ralink/rt305x.c
  28. @@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
  29. .wdt_reset = rt305x_wdt_reset,
  30. };
  31. +static unsigned long rt5350_get_mem_size(void)
  32. +{
  33. + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  34. + unsigned long ret;
  35. + u32 t;
  36. +
  37. + t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
  38. + t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
  39. + RT5350_SYSCFG0_DRAM_SIZE_MASK;
  40. +
  41. + switch (t) {
  42. + case RT5350_SYSCFG0_DRAM_SIZE_2M:
  43. + ret = 2;
  44. + break;
  45. + case RT5350_SYSCFG0_DRAM_SIZE_8M:
  46. + ret = 8;
  47. + break;
  48. + case RT5350_SYSCFG0_DRAM_SIZE_16M:
  49. + ret = 16;
  50. + break;
  51. + case RT5350_SYSCFG0_DRAM_SIZE_32M:
  52. + ret = 32;
  53. + break;
  54. + case RT5350_SYSCFG0_DRAM_SIZE_64M:
  55. + ret = 64;
  56. + break;
  57. + default:
  58. + panic("rt5350: invalid DRAM size: %u", t);
  59. + break;
  60. + }
  61. +
  62. + return ret;
  63. +}
  64. +
  65. void __init ralink_clk_init(void)
  66. {
  67. unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  68. @@ -252,4 +286,15 @@ void prom_soc_init(struct ralink_soc_inf
  69. name,
  70. (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  71. (id & CHIP_ID_REV_MASK));
  72. +
  73. + soc_info->mem_base = RT305X_SDRAM_BASE;
  74. + if (soc_is_rt5350()) {
  75. + soc_info->mem_size = rt5350_get_mem_size();
  76. + } else if (soc_is_rt305x() || soc_is_rt3350()) {
  77. + soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
  78. + soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
  79. + } else if (soc_is_rt3352()) {
  80. + soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
  81. + soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
  82. + }
  83. }