0140-MIPS-ralink-DTS-file-updates.patch 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978
  1. From cee339922876e924295c27e274923d1b381f5057 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Tue, 30 Apr 2013 17:27:46 +0200
  4. Subject: [PATCH 140/164] MIPS: ralink DTS file updates
  5. Signed-off-by: John Crispin <[email protected]>
  6. ---
  7. arch/mips/ralink/Kconfig | 8 +
  8. arch/mips/ralink/dts/Makefile | 2 +
  9. arch/mips/ralink/dts/mt7620a.dtsi | 238 ++++++++++++++++++++++++-
  10. arch/mips/ralink/dts/mt7620a_eval.dts | 111 ++++++++++++
  11. arch/mips/ralink/dts/mt7620a_mt7610e_eval.dts | 99 ++++++++++
  12. arch/mips/ralink/dts/rt2880.dtsi | 17 ++
  13. arch/mips/ralink/dts/rt2880_eval.dts | 6 +
  14. arch/mips/ralink/dts/rt3050.dtsi | 31 +++-
  15. arch/mips/ralink/dts/rt3052_eval.dts | 19 +-
  16. arch/mips/ralink/dts/rt5350.dtsi | 227 +++++++++++++++++++++++
  17. arch/mips/ralink/dts/rt5350_eval.dts | 69 +++++++
  18. 11 files changed, 824 insertions(+), 3 deletions(-)
  19. create mode 100644 arch/mips/ralink/dts/mt7620a_mt7610e_eval.dts
  20. create mode 100644 arch/mips/ralink/dts/rt5350.dtsi
  21. create mode 100644 arch/mips/ralink/dts/rt5350_eval.dts
  22. --- a/arch/mips/ralink/Kconfig
  23. +++ b/arch/mips/ralink/Kconfig
  24. @@ -42,6 +42,10 @@ choice
  25. bool "RT305x eval kit"
  26. depends on SOC_RT305X
  27. + config DTB_RT5350_EVAL
  28. + bool "RT5350 eval kit"
  29. + depends on SOC_RT305X
  30. +
  31. config DTB_RT3883_EVAL
  32. bool "RT3883 eval kit"
  33. depends on SOC_RT3883
  34. @@ -50,6 +54,10 @@ choice
  35. bool "MT7620A eval kit"
  36. depends on SOC_MT7620
  37. + config DTB_MT7620A_MT7610E_EVAL
  38. + bool "MT7620A + MT7610E eval kit"
  39. + depends on SOC_MT7620
  40. +
  41. endchoice
  42. endif
  43. --- a/arch/mips/ralink/dts/Makefile
  44. +++ b/arch/mips/ralink/dts/Makefile
  45. @@ -1,4 +1,6 @@
  46. obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
  47. obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
  48. +obj-$(CONFIG_DTB_RT5350_EVAL) := rt5350_eval.dtb.o
  49. obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
  50. obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
  51. +obj-$(CONFIG_DTB_MT7620A_MT7610E_EVAL) := mt7620a_mt7610e_eval.dtb.o
  52. --- a/arch/mips/ralink/dts/mt7620a.dtsi
  53. +++ b/arch/mips/ralink/dts/mt7620a.dtsi
  54. @@ -25,14 +25,36 @@
  55. #size-cells = <1>;
  56. sysc@0 {
  57. - compatible = "ralink,mt7620a-sysc";
  58. + compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc";
  59. reg = <0x0 0x100>;
  60. };
  61. + timer@100 {
  62. + compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
  63. + reg = <0x100 0x20>;
  64. +
  65. + interrupt-parent = <&intc>;
  66. + interrupts = <1>;
  67. + };
  68. +
  69. + watchdog@120 {
  70. + compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
  71. + reg = <0x120 0x10>;
  72. +
  73. + resets = <&rstctrl 8>;
  74. + reset-names = "wdt";
  75. +
  76. + interrupt-parent = <&intc>;
  77. + interrupts = <1>;
  78. + };
  79. +
  80. intc: intc@200 {
  81. compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
  82. reg = <0x200 0x100>;
  83. + resets = <&rstctrl 19>;
  84. + reset-names = "intc";
  85. +
  86. interrupt-controller;
  87. #interrupt-cells = <1>;
  88. @@ -43,16 +65,230 @@
  89. memc@300 {
  90. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  91. reg = <0x300 0x100>;
  92. +
  93. + resets = <&rstctrl 20>;
  94. + reset-names = "mc";
  95. +
  96. + interrupt-parent = <&intc>;
  97. + interrupts = <3>;
  98. + };
  99. +
  100. + uart@500 {
  101. + compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  102. + reg = <0x500 0x100>;
  103. +
  104. + resets = <&rstctrl 12>;
  105. + reset-names = "uart";
  106. +
  107. + interrupt-parent = <&intc>;
  108. + interrupts = <5>;
  109. +
  110. + reg-shift = <2>;
  111. +
  112. + status = "disabled";
  113. + };
  114. +
  115. + gpio0: gpio@600 {
  116. + compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  117. + reg = <0x600 0x34>;
  118. +
  119. + resets = <&rstctrl 13>;
  120. + reset-names = "pio";
  121. +
  122. + interrupt-parent = <&intc>;
  123. + interrupts = <6>;
  124. +
  125. + gpio-controller;
  126. + #gpio-cells = <2>;
  127. +
  128. + ralink,gpio-base = <0>;
  129. + ralink,num-gpios = <24>;
  130. + ralink,register-map = [ 00 04 08 0c
  131. + 20 24 28 2c
  132. + 30 34 ];
  133. +
  134. + status = "disabled";
  135. + };
  136. +
  137. + gpio1: gpio@638 {
  138. + compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  139. + reg = <0x638 0x24>;
  140. +
  141. + interrupt-parent = <&intc>;
  142. + interrupts = <6>;
  143. +
  144. + gpio-controller;
  145. + #gpio-cells = <2>;
  146. +
  147. + ralink,gpio-base = <24>;
  148. + ralink,num-gpios = <16>;
  149. + ralink,register-map = [ 00 04 08 0c
  150. + 10 14 18 1c
  151. + 20 24 ];
  152. +
  153. + status = "disabled";
  154. + };
  155. +
  156. + gpio2: gpio@660 {
  157. + compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  158. + reg = <0x660 0x24>;
  159. +
  160. + interrupt-parent = <&intc>;
  161. + interrupts = <6>;
  162. +
  163. + gpio-controller;
  164. + #gpio-cells = <2>;
  165. +
  166. + ralink,gpio-base = <40>;
  167. + ralink,num-gpios = <32>;
  168. + ralink,register-map = [ 00 04 08 0c
  169. + 10 14 18 1c
  170. + 20 24 ];
  171. +
  172. + status = "disabled";
  173. + };
  174. +
  175. + i2c@900 {
  176. + compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c";
  177. + reg = <0x900 0x100>;
  178. +
  179. + resets = <&rstctrl 16>;
  180. + reset-names = "i2c";
  181. +
  182. + #address-cells = <1>;
  183. + #size-cells = <0>;
  184. +
  185. + status = "disabled";
  186. + };
  187. +
  188. + spi@b00 {
  189. + compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
  190. + reg = <0xb00 0x100>;
  191. +
  192. + resets = <&rstctrl 18>;
  193. + reset-names = "spi";
  194. +
  195. + #address-cells = <1>;
  196. + #size-cells = <1>;
  197. +
  198. + status = "disabled";
  199. };
  200. uartlite@c00 {
  201. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  202. reg = <0xc00 0x100>;
  203. + resets = <&rstctrl 19>;
  204. + reset-names = "uartl";
  205. +
  206. interrupt-parent = <&intc>;
  207. interrupts = <12>;
  208. reg-shift = <2>;
  209. };
  210. +
  211. + systick@d00 {
  212. + compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
  213. + reg = <0xd00 0x10>;
  214. +
  215. + resets = <&rstctrl 28>;
  216. + reset-names = "intc";
  217. +
  218. + interrupt-parent = <&cpuintc>;
  219. + interrupts = <7>;
  220. + };
  221. +
  222. + gdma@2800 {
  223. + compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
  224. + reg = <0x2800 0x800>;
  225. +
  226. + resets = <&rstctrl 14>;
  227. + reset-names = "dma";
  228. +
  229. + interrupt-parent = <&intc>;
  230. + interrupts = <7>;
  231. + };
  232. + };
  233. +
  234. + rstctrl: rstctrl {
  235. + compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  236. + #reset-cells = <1>;
  237. + };
  238. +
  239. + ubsphy {
  240. + compatible = "ralink,mt7620a-usbphy";
  241. +
  242. + resets = <&rstctrl 22 &rstctrl 25>;
  243. + reset-names = "host", "device";
  244. + };
  245. +
  246. + ethernet@10100000 {
  247. + compatible = "ralink,mt7620a-eth";
  248. + reg = <0x10100000 10000>;
  249. +
  250. + #address-cells = <1>;
  251. + #size-cells = <0>;
  252. +
  253. + interrupt-parent = <&cpuintc>;
  254. + interrupts = <5>;
  255. +
  256. + status = "disabled";
  257. +
  258. + mdio-bus {
  259. + #address-cells = <1>;
  260. + #size-cells = <0>;
  261. +
  262. + status = "disabled";
  263. + };
  264. + };
  265. +
  266. + gsw@10110000 {
  267. + compatible = "ralink,mt7620a-gsw";
  268. + reg = <0x10110000 8000>;
  269. +
  270. + interrupt-parent = <&intc>;
  271. + interrupts = <17>;
  272. +
  273. + status = "disabled";
  274. + };
  275. +
  276. + sdhci@10130000 {
  277. + compatible = "ralink,mt7620a-sdhci";
  278. + reg = <0x10130000 4000>;
  279. +
  280. + interrupt-parent = <&intc>;
  281. + interrupts = <14>;
  282. +
  283. + status = "disabled";
  284. + };
  285. +
  286. + ehci@101c0000 {
  287. + compatible = "ralink,rt3xxx-ehci";
  288. + reg = <0x101c0000 0x1000>;
  289. +
  290. + interrupt-parent = <&intc>;
  291. + interrupts = <18>;
  292. + };
  293. +
  294. + ohci@101c1000 {
  295. + compatible = "ralink,rt3xxx-ohci";
  296. + reg = <0x101c1000 0x1000>;
  297. +
  298. + interrupt-parent = <&intc>;
  299. + interrupts = <18>;
  300. + };
  301. +
  302. + pcie@10140000 {
  303. + compatible = "ralink,mt7620a-pci";
  304. + reg = <0x10140000 0x100
  305. + 0x10142000 0x100>;
  306. +
  307. + resets = <&rstctrl 26>;
  308. + reset-names = "pcie0";
  309. +
  310. + interrupt-parent = <&cpuintc>;
  311. + interrupts = <4>;
  312. +
  313. + status = "disabled";
  314. };
  315. };
  316. --- a/arch/mips/ralink/dts/mt7620a_eval.dts
  317. +++ b/arch/mips/ralink/dts/mt7620a_eval.dts
  318. @@ -13,4 +13,115 @@
  319. chosen {
  320. bootargs = "console=ttyS0,57600";
  321. };
  322. +
  323. + palmbus@10000000 {
  324. + sysc@0 {
  325. + ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
  326. + ralink,gpiomux = "i2c", "jtag";
  327. + ralink,uartmux = "gpio";
  328. + ralink,wdtmux = <1>;
  329. + };
  330. +
  331. + gpio0: gpio@600 {
  332. + status = "okay";
  333. + };
  334. +
  335. + spi@b00 {
  336. + status = "okay";
  337. +
  338. + m25p80@0 {
  339. + #address-cells = <1>;
  340. + #size-cells = <1>;
  341. + compatible = "en25q64";
  342. + reg = <0 0>;
  343. + linux,modalias = "m25p80", "en25q64";
  344. + spi-max-frequency = <10000000>;
  345. +
  346. + partition@0 {
  347. + label = "u-boot";
  348. + reg = <0x0 0x30000>;
  349. + read-only;
  350. + };
  351. +
  352. + partition@30000 {
  353. + label = "u-boot-env";
  354. + reg = <0x30000 0x10000>;
  355. + read-only;
  356. + };
  357. +
  358. + factory: partition@40000 {
  359. + label = "factory";
  360. + reg = <0x40000 0x10000>;
  361. + read-only;
  362. + };
  363. +
  364. + partition@50000 {
  365. + label = "firmware";
  366. + reg = <0x50000 0x7b0000>;
  367. + };
  368. + };
  369. + };
  370. + };
  371. +
  372. + ethernet@10100000 {
  373. + status = "okay";
  374. +
  375. + port@4 {
  376. + compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
  377. + reg = <4>;
  378. + phy-mode = "rgmii";
  379. + phy-handle = <&phy4>;
  380. + };
  381. +
  382. + port@5 {
  383. + compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
  384. + reg = <5>;
  385. + phy-mode = "rgmii";
  386. + phy-handle = <&phy5>;
  387. + };
  388. +
  389. + mdio-bus {
  390. + status = "okay";
  391. +
  392. + phy4: ethernet-phy@4 {
  393. + reg = <4>;
  394. + phy-mode = "rgmii";
  395. + };
  396. +
  397. + phy5: ethernet-phy@5 {
  398. + reg = <5>;
  399. + phy-mode = "rgmii";
  400. + };
  401. + };
  402. + };
  403. +
  404. + gsw@10110000 {
  405. + status = "okay";
  406. + ralink,port4 = "gmac";
  407. + };
  408. +
  409. + sdhci@10130000 {
  410. + status = "okay";
  411. + };
  412. +
  413. + pcie@10140000 {
  414. + status = "okay";
  415. + };
  416. +
  417. + gpio-keys-polled {
  418. + compatible = "gpio-keys";
  419. + #address-cells = <1>;
  420. + #size-cells = <0>;
  421. + poll-interval = <20>;
  422. + s2 {
  423. + label = "S2";
  424. + gpios = <&gpio0 1 1>;
  425. + linux,code = <0x100>;
  426. + };
  427. + s3 {
  428. + label = "S3";
  429. + gpios = <&gpio0 2 1>;
  430. + linux,code = <0x101>;
  431. + };
  432. + };
  433. };
  434. --- /dev/null
  435. +++ b/arch/mips/ralink/dts/mt7620a_mt7610e_eval.dts
  436. @@ -0,0 +1,99 @@
  437. +/dts-v1/;
  438. +
  439. +/include/ "mt7620a.dtsi"
  440. +
  441. +/ {
  442. + compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  443. + model = "Ralink MT7620A evaluation board";
  444. +
  445. + memory@0 {
  446. + reg = <0x0 0x2000000>;
  447. + };
  448. +
  449. + chosen {
  450. + bootargs = "console=ttyS0,57600";
  451. + };
  452. +
  453. + palmbus@10000000 {
  454. + sysc@0 {
  455. + ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
  456. + ralink,gpiomux = "i2c", "jtag";
  457. + ralink,uartmux = "gpio";
  458. + ralink,wdtmux = <1>;
  459. + };
  460. +
  461. + gpio0: gpio@600 {
  462. + status = "okay";
  463. + };
  464. +
  465. + spi@b00 {
  466. + status = "okay";
  467. +
  468. + m25p80@0 {
  469. + #address-cells = <1>;
  470. + #size-cells = <1>;
  471. + compatible = "en25q64";
  472. + reg = <0 0>;
  473. + linux,modalias = "m25p80", "en25q64";
  474. + spi-max-frequency = <10000000>;
  475. +
  476. + partition@0 {
  477. + label = "u-boot";
  478. + reg = <0x0 0x30000>;
  479. + read-only;
  480. + };
  481. +
  482. + partition@30000 {
  483. + label = "u-boot-env";
  484. + reg = <0x30000 0x10000>;
  485. + read-only;
  486. + };
  487. +
  488. + factory: partition@40000 {
  489. + label = "factory";
  490. + reg = <0x40000 0x10000>;
  491. + read-only;
  492. + };
  493. +
  494. + partition@50000 {
  495. + label = "firmware";
  496. + reg = <0x50000 0x7b0000>;
  497. + };
  498. + };
  499. + };
  500. + };
  501. +
  502. + ethernet@10100000 {
  503. + status = "okay";
  504. + };
  505. +
  506. + gsw@10110000 {
  507. + status = "okay";
  508. + ralink,port4 = "ephy";
  509. + };
  510. +
  511. + sdhci@10130000 {
  512. + status = "okay";
  513. + };
  514. +
  515. + pcie@10140000 {
  516. + status = "okay";
  517. + };
  518. +
  519. + gpio-keys-polled {
  520. + compatible = "gpio-keys";
  521. + #address-cells = <1>;
  522. + #size-cells = <0>;
  523. + poll-interval = <20>;
  524. + wps {
  525. + label = "wps";
  526. + gpios = <&gpio0 12 1>;
  527. + linux,code = <0x100>;
  528. + };
  529. + reset {
  530. + label = "reset";
  531. + gpios = <&gpio0 13 1>;
  532. + linux,code = <0x101>;
  533. + };
  534. + };
  535. +};
  536. --- a/arch/mips/ralink/dts/rt2880.dtsi
  537. +++ b/arch/mips/ralink/dts/rt2880.dtsi
  538. @@ -55,4 +55,21 @@
  539. reg-shift = <2>;
  540. };
  541. };
  542. +
  543. + ethernet@400000 {
  544. + compatible = "ralink,rt2880-eth";
  545. + reg = <0x00400000 10000>;
  546. +
  547. + interrupt-parent = <&cpuintc>;
  548. + interrupts = <5>;
  549. +
  550. + status = "disabled";
  551. +
  552. + mdio-bus {
  553. + #address-cells = <1>;
  554. + #size-cells = <0>;
  555. +
  556. + status = "disabled";
  557. + };
  558. + };
  559. };
  560. --- a/arch/mips/ralink/dts/rt2880_eval.dts
  561. +++ b/arch/mips/ralink/dts/rt2880_eval.dts
  562. @@ -43,4 +43,10 @@
  563. reg = <0x50000 0x3b0000>;
  564. };
  565. };
  566. +
  567. + ethernet@400000 {
  568. + status = "okay";
  569. +
  570. + ralink,fixed-link = <1000 1 1 1>;
  571. + };
  572. };
  573. --- a/arch/mips/ralink/dts/rt3050.dtsi
  574. +++ b/arch/mips/ralink/dts/rt3050.dtsi
  575. @@ -1,7 +1,7 @@
  576. / {
  577. #address-cells = <1>;
  578. #size-cells = <1>;
  579. - compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
  580. + compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
  581. cpus {
  582. cpu@0 {
  583. @@ -45,6 +45,15 @@
  584. reg = <0x300 0x100>;
  585. };
  586. + i2c@900 {
  587. + compatible = "link,rt3052-i2c", "ralink,rt2880-i2c";
  588. + reg = <0x900 0x100>;
  589. + #address-cells = <1>;
  590. + #size-cells = <0>;
  591. +
  592. + status = "disabled";
  593. + };
  594. +
  595. uartlite@c00 {
  596. compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
  597. reg = <0xc00 0x100>;
  598. @@ -55,4 +64,24 @@
  599. reg-shift = <2>;
  600. };
  601. };
  602. +
  603. + ethernet@10100000 {
  604. + compatible = "ralink,rt3050-eth";
  605. + reg = <0x10100000 10000>;
  606. +
  607. + interrupt-parent = <&cpuintc>;
  608. + interrupts = <5>;
  609. +
  610. + status = "disabled";
  611. + };
  612. +
  613. + esw@10110000 {
  614. + compatible = "ralink,rt3050-esw";
  615. + reg = <0x10110000 8000>;
  616. +
  617. + interrupt-parent = <&intc>;
  618. + interrupts = <17>;
  619. +
  620. + status = "disabled";
  621. + };
  622. };
  623. --- a/arch/mips/ralink/dts/rt3052_eval.dts
  624. +++ b/arch/mips/ralink/dts/rt3052_eval.dts
  625. @@ -3,7 +3,7 @@
  626. /include/ "rt3050.dtsi"
  627. / {
  628. - compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
  629. + compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc", "ralink,rt5350-soc";
  630. model = "Ralink RT3052 evaluation board";
  631. memory@0 {
  632. @@ -14,6 +14,14 @@
  633. bootargs = "console=ttyS0,57600";
  634. };
  635. + palmbus@10000000 {
  636. + sysc@0 {
  637. + ralink,pinmux = "i2c", "spi", "uartlite", "jtag", "mdio", "sdram", "rgmii";
  638. + ralink,uartmux = "gpio";
  639. + ralink,wdtmux = <1>;
  640. + };
  641. + };
  642. +
  643. cfi@1f000000 {
  644. compatible = "cfi-flash";
  645. reg = <0x1f000000 0x800000>;
  646. @@ -43,4 +51,13 @@
  647. reg = <0x50000 0x7b0000>;
  648. };
  649. };
  650. +
  651. + ethernet@10100000 {
  652. + status = "okay";
  653. + };
  654. +
  655. + esw@10110000 {
  656. + status = "okay";
  657. + ralink,portmap = <0x2f>;
  658. + };
  659. };
  660. --- /dev/null
  661. +++ b/arch/mips/ralink/dts/rt5350.dtsi
  662. @@ -0,0 +1,227 @@
  663. +/ {
  664. + #address-cells = <1>;
  665. + #size-cells = <1>;
  666. + compatible = "ralink,rt5350-soc";
  667. +
  668. + cpus {
  669. + cpu@0 {
  670. + compatible = "mips,mips24KEc";
  671. + };
  672. + };
  673. +
  674. + cpuintc: cpuintc@0 {
  675. + #address-cells = <0>;
  676. + #interrupt-cells = <1>;
  677. + interrupt-controller;
  678. + compatible = "mti,cpu-interrupt-controller";
  679. + };
  680. +
  681. + palmbus@10000000 {
  682. + compatible = "palmbus";
  683. + reg = <0x10000000 0x200000>;
  684. + ranges = <0x0 0x10000000 0x1FFFFF>;
  685. +
  686. + #address-cells = <1>;
  687. + #size-cells = <1>;
  688. +
  689. + sysc@0 {
  690. + compatible = "ralink,rt5350-sysc", "ralink,rt3050-sysc";
  691. + reg = <0x0 0x100>;
  692. + };
  693. +
  694. + timer@100 {
  695. + compatible = "ralink,rt5350-timer", "ralink,rt2880-timer";
  696. + reg = <0x100 0x20>;
  697. +
  698. + interrupt-parent = <&intc>;
  699. + interrupts = <1>;
  700. + };
  701. +
  702. + watchdog@120 {
  703. + compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt";
  704. + reg = <0x120 0x10>;
  705. +
  706. + resets = <&rstctrl 8>;
  707. + reset-names = "wdt";
  708. +
  709. + interrupt-parent = <&intc>;
  710. + interrupts = <1>;
  711. + };
  712. +
  713. + intc: intc@200 {
  714. + compatible = "ralink,rt5350-intc", "ralink,rt2880-intc";
  715. + reg = <0x200 0x100>;
  716. +
  717. + resets = <&rstctrl 19>;
  718. + reset-names = "intc";
  719. +
  720. + interrupt-controller;
  721. + #interrupt-cells = <1>;
  722. +
  723. + interrupt-parent = <&cpuintc>;
  724. + interrupts = <2>;
  725. + };
  726. +
  727. + memc@300 {
  728. + compatible = "ralink,rt5350-memc", "ralink,rt3050-memc";
  729. + reg = <0x300 0x100>;
  730. +
  731. + resets = <&rstctrl 20>;
  732. + reset-names = "mc";
  733. +
  734. + interrupt-parent = <&intc>;
  735. + interrupts = <3>;
  736. + };
  737. +
  738. + uart@500 {
  739. + compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
  740. + reg = <0x500 0x100>;
  741. +
  742. + resets = <&rstctrl 12>;
  743. + reset-names = "uart";
  744. +
  745. + interrupt-parent = <&intc>;
  746. + interrupts = <5>;
  747. +
  748. + reg-shift = <2>;
  749. +
  750. + status = "disabled";
  751. + };
  752. +
  753. + gpio0: gpio@600 {
  754. + compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
  755. + reg = <0x600 0x34>;
  756. +
  757. + resets = <&rstctrl 13>;
  758. + reset-names = "pio";
  759. +
  760. + interrupt-parent = <&intc>;
  761. + interrupts = <6>;
  762. +
  763. + gpio-controller;
  764. + #gpio-cells = <2>;
  765. +
  766. + ralink,gpio-base = <0>;
  767. + ralink,num-gpios = <24>;
  768. + ralink,register-map = [ 00 04 08 0c
  769. + 20 24 28 2c
  770. + 30 34 ];
  771. +
  772. + status = "disabled";
  773. + };
  774. +
  775. + gpio1: gpio@638 {
  776. + compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
  777. + reg = <0x638 0x24>;
  778. +
  779. + interrupt-parent = <&intc>;
  780. + interrupts = <6>;
  781. +
  782. + gpio-controller;
  783. + #gpio-cells = <2>;
  784. +
  785. + ralink,gpio-base = <24>;
  786. + ralink,num-gpios = <16>;
  787. + ralink,register-map = [ 00 04 08 0c
  788. + 10 14 18 1c
  789. + 20 24 ];
  790. +
  791. + status = "disabled";
  792. + };
  793. +
  794. + i2c@900 {
  795. + compatible = "link,rt5350-i2c", "ralink,rt2880-i2c";
  796. + reg = <0x900 0x100>;
  797. +
  798. + resets = <&rstctrl 16>;
  799. + reset-names = "i2c";
  800. +
  801. + #address-cells = <1>;
  802. + #size-cells = <0>;
  803. +
  804. + status = "disabled";
  805. + };
  806. +
  807. + spi@b00 {
  808. + compatible = "ralink,rt5350-spi", "ralink,rt2880-spi";
  809. + reg = <0xb00 0x100>;
  810. +
  811. + resets = <&rstctrl 18>;
  812. + reset-names = "spi";
  813. +
  814. + #address-cells = <1>;
  815. + #size-cells = <1>;
  816. +
  817. + status = "disabled";
  818. + };
  819. +
  820. + uartlite@c00 {
  821. + compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
  822. + reg = <0xc00 0x100>;
  823. +
  824. + resets = <&rstctrl 19>;
  825. + reset-names = "uartl";
  826. +
  827. + interrupt-parent = <&intc>;
  828. + interrupts = <12>;
  829. +
  830. + reg-shift = <2>;
  831. + };
  832. +
  833. + systick@d00 {
  834. + compatible = "ralink,rt5350-systick", "ralink,cevt-systick";
  835. + reg = <0xd00 0x10>;
  836. +
  837. + interrupt-parent = <&cpuintc>;
  838. + interrupts = <7>;
  839. + };
  840. + };
  841. +
  842. + rstctrl: rstctrl {
  843. + compatible = "ralink,rt5350-reset", "ralink,rt2880-reset";
  844. + #reset-cells = <1>;
  845. + };
  846. +
  847. + ubsphy {
  848. + compatible = "ralink,rt3xxx-usbphy";
  849. +
  850. + resets = <&rstctrl 22 &rstctrl 25>;
  851. + reset-names = "host", "device";
  852. + };
  853. +
  854. + ethernet@10100000 {
  855. + compatible = "ralink,rt5350-eth";
  856. + reg = <0x10100000 10000>;
  857. +
  858. + interrupt-parent = <&cpuintc>;
  859. + interrupts = <5>;
  860. +
  861. + status = "disabled";
  862. + };
  863. +
  864. + esw@10110000 {
  865. + compatible = "ralink,rt3050-esw";
  866. + reg = <0x10110000 8000>;
  867. +
  868. + interrupt-parent = <&intc>;
  869. + interrupts = <17>;
  870. +
  871. + status = "disabled";
  872. + };
  873. +
  874. + ehci@101c0000 {
  875. + compatible = "ralink,rt3xxx-ehci";
  876. + reg = <0x101c0000 0x1000>;
  877. +
  878. + interrupt-parent = <&intc>;
  879. + interrupts = <18>;
  880. + };
  881. +
  882. + ohci@101c1000 {
  883. + compatible = "ralink,rt3xxx-ohci";
  884. + reg = <0x101c1000 0x1000>;
  885. +
  886. + interrupt-parent = <&intc>;
  887. + interrupts = <18>;
  888. + };
  889. +};
  890. --- /dev/null
  891. +++ b/arch/mips/ralink/dts/rt5350_eval.dts
  892. @@ -0,0 +1,69 @@
  893. +/dts-v1/;
  894. +
  895. +/include/ "rt5350.dtsi"
  896. +
  897. +/ {
  898. + compatible = "ralink,rt5350-eval-board", "ralink,rt5350-soc";
  899. + model = "Ralink RT5350 evaluation board";
  900. +
  901. + chosen {
  902. + bootargs = "console=ttyS0,57600";
  903. + };
  904. +
  905. + palmbus@10000000 {
  906. + sysc@0 {
  907. + ralink,pinmux = "i2c", "spi", "uartlite", "jtag", "mdio", "sdram", "rgmii";
  908. + ralink,uartmux = "gpio";
  909. + ralink,wdtmux = <1>;
  910. + };
  911. +
  912. + gpio0: gpio@600 {
  913. + status = "okay";
  914. + };
  915. +
  916. + spi@b00 {
  917. + status = "okay";
  918. +
  919. + m25p80@0 {
  920. + #address-cells = <1>;
  921. + #size-cells = <1>;
  922. + compatible = "en25q64";
  923. + reg = <0 0>;
  924. + linux,modalias = "m25p80", "mx25l3205d";
  925. + spi-max-frequency = <10000000>;
  926. +
  927. + partition@0 {
  928. + label = "u-boot";
  929. + reg = <0x0 0x30000>;
  930. + read-only;
  931. + };
  932. +
  933. + partition@30000 {
  934. + label = "u-boot-env";
  935. + reg = <0x30000 0x10000>;
  936. + read-only;
  937. + };
  938. +
  939. + factory: partition@40000 {
  940. + label = "factory";
  941. + reg = <0x40000 0x10000>;
  942. + read-only;
  943. + };
  944. +
  945. + partition@50000 {
  946. + label = "firmware";
  947. + reg = <0x50000 0x3b0000>;
  948. + };
  949. + };
  950. + };
  951. + };
  952. +
  953. + ethernet@10100000 {
  954. + status = "okay";
  955. + };
  956. +
  957. + esw@10110000 {
  958. + status = "okay";
  959. + ralink,portmap = <0x2f>;
  960. + };
  961. +};