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- From 478b09fa2c00cbc40d25bc061befdf11f04a27ad Mon Sep 17 00:00:00 2001
- From: Sergio Paracuellos <[email protected]>
- Date: Thu, 10 Feb 2022 10:48:58 +0100
- Subject: [PATCH 1/2] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
- Make system controller a reset provider for all the peripherals in the
- MT7621 SoC adding '#reset-cells' property.
- Acked-by: Rob Herring <[email protected]>
- Acked-by: Stephen Boyd <[email protected]>
- Signed-off-by: Sergio Paracuellos <[email protected]>
- Link: https://lore.kernel.org/r/[email protected]
- Signed-off-by: Greg Kroah-Hartman <[email protected]>
- ---
- .../devicetree/bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
- --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
- +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
- @@ -22,6 +22,11 @@ description: |
-
- The clocks are provided inside a system controller node.
-
- + This node is also a reset provider for all the peripherals.
- +
- + Reset related bits are defined in:
- + [2]: <include/dt-bindings/reset/mt7621-reset.h>.
- +
- properties:
- compatible:
- items:
- @@ -37,6 +42,12 @@ properties:
- clocks.
- const: 1
-
- + "#reset-cells":
- + description:
- + The first cell indicates the reset bit within the register, see
- + [2] for available resets.
- + const: 1
- +
- ralink,memctl:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
- @@ -61,6 +72,7 @@ examples:
- compatible = "mediatek,mt7621-sysc", "syscon";
- reg = <0x0 0x100>;
- #clock-cells = <1>;
- + #reset-cells = <1>;
- ralink,memctl = <&memc>;
- clock-output-names = "xtal", "cpu", "bus",
- "50m", "125m", "150m",
|
