ipq8072-ax9000.dts 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2021, Robert Marko <[email protected]> */
  3. /dts-v1/;
  4. #include "ipq8074.dtsi"
  5. #include "ipq8074-hk-cpu.dtsi"
  6. #include "ipq8074-ess.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/input/input.h>
  9. #include <dt-bindings/leds/common.h>
  10. / {
  11. model = "Xiaomi AX9000";
  12. compatible = "xiaomi,ax9000", "qcom,ipq8074";
  13. aliases {
  14. serial0 = &blsp1_uart5;
  15. led-boot = &led_system_yellow;
  16. led-failsafe = &led_system_yellow;
  17. led-running = &led_system_blue;
  18. led-upgrade = &led_system_yellow;
  19. label-mac-device = &dp5;
  20. };
  21. chosen {
  22. stdout-path = "serial0:115200n8";
  23. bootargs-append = " root=/dev/ubiblock0_0";
  24. };
  25. keys {
  26. compatible = "gpio-keys";
  27. reset {
  28. label = "reset";
  29. gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  30. linux,code = <KEY_RESTART>;
  31. };
  32. wps {
  33. label = "wps"; /* Labeled Mesh on the device */
  34. gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
  35. linux,code = <KEY_WPS_BUTTON>;
  36. };
  37. };
  38. leds {
  39. compatible = "gpio-leds";
  40. led_system_blue: system-blue {
  41. gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
  42. color = <LED_COLOR_ID_BLUE>;
  43. };
  44. led_system_yellow: system-yellow {
  45. gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
  46. color = <LED_COLOR_ID_YELLOW>;
  47. };
  48. network-yellow {
  49. gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
  50. color = <LED_COLOR_ID_YELLOW>;
  51. };
  52. network-blue {
  53. gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
  54. color = <LED_COLOR_ID_BLUE>;
  55. };
  56. top-red {
  57. gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
  58. color = <LED_COLOR_ID_RED>;
  59. default-state = "keep";
  60. };
  61. top-green {
  62. gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
  63. color = <LED_COLOR_ID_GREEN>;
  64. default-state = "keep";
  65. };
  66. top-blue {
  67. gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
  68. color = <LED_COLOR_ID_BLUE>;
  69. default-state = "keep";
  70. };
  71. };
  72. };
  73. &tlmm {
  74. mdio_pins: mdio-pins {
  75. mdc {
  76. pins = "gpio68";
  77. function = "mdc";
  78. drive-strength = <8>;
  79. bias-pull-up;
  80. };
  81. mdio {
  82. pins = "gpio69";
  83. function = "mdio";
  84. drive-strength = <8>;
  85. bias-pull-up;
  86. };
  87. };
  88. i2c_pins: i2c-pins {
  89. pins = "gpio0", "gpio2";
  90. function = "blsp5_i2c";
  91. drive-strength = <8>;
  92. bias-disable;
  93. };
  94. };
  95. &blsp1_uart5 {
  96. status = "okay";
  97. };
  98. &blsp1_i2c6 {
  99. status = "okay";
  100. pinctrl-0 = <&i2c_pins>;
  101. pinctrl-names = "default";
  102. };
  103. &prng {
  104. status = "okay";
  105. };
  106. &cryptobam {
  107. status = "okay";
  108. };
  109. &crypto {
  110. status = "okay";
  111. };
  112. &qpic_bam {
  113. status = "okay";
  114. };
  115. &qpic_nand {
  116. status = "okay";
  117. /*
  118. * Bootloader will find the NAND DT node by the compatible and
  119. * then "fixup" it by adding the partitions from the SMEM table
  120. * using the legacy bindings thus making it impossible for us
  121. * to change the partition table or utilize NVMEM for calibration.
  122. * So add a dummy partitions node that bootloader will populate
  123. * and set it as disabled so the kernel ignores it instead of
  124. * printing warnings due to the broken way bootloader adds the
  125. * partitions.
  126. */
  127. partitions {
  128. status = "disabled";
  129. };
  130. nand@0 {
  131. reg = <0>;
  132. nand-ecc-strength = <4>;
  133. nand-ecc-step-size = <512>;
  134. nand-bus-width = <8>;
  135. partitions {
  136. compatible = "fixed-partitions";
  137. #address-cells = <1>;
  138. #size-cells = <1>;
  139. partition@0 {
  140. label = "0:sbl1";
  141. reg = <0x0 0x100000>;
  142. read-only;
  143. };
  144. partition@100000 {
  145. label = "0:mibib";
  146. reg = <0x100000 0x100000>;
  147. read-only;
  148. };
  149. partition@200000 {
  150. label = "0:bootconfig";
  151. reg = <0x200000 0x80000>;
  152. read-only;
  153. };
  154. partition@280000 {
  155. label = "0:bootconfig1";
  156. reg = <0x280000 0x80000>;
  157. read-only;
  158. };
  159. partition@300000 {
  160. label = "0:qsee";
  161. reg = <0x300000 0x300000>;
  162. read-only;
  163. };
  164. partition@600000 {
  165. label = "0:qsee_1";
  166. reg = <0x600000 0x300000>;
  167. read-only;
  168. };
  169. partition@900000 {
  170. label = "0:devcfg";
  171. reg = <0x900000 0x80000>;
  172. read-only;
  173. };
  174. partition@980000 {
  175. label = "0:devcfg_1";
  176. reg = <0x980000 0x80000>;
  177. read-only;
  178. };
  179. partition@a00000 {
  180. label = "0:apdp";
  181. reg = <0xa00000 0x80000>;
  182. read-only;
  183. };
  184. partition@a80000 {
  185. label = "0:apdp_1";
  186. reg = <0xa80000 0x80000>;
  187. read-only;
  188. };
  189. partition@b00000 {
  190. label = "0:rpm";
  191. reg = <0xb00000 0x80000>;
  192. read-only;
  193. };
  194. partition@b80000 {
  195. label = "0:rpm_1";
  196. reg = <0xb80000 0x80000>;
  197. read-only;
  198. };
  199. partition@c00000 {
  200. label = "0:cdt";
  201. reg = <0xc00000 0x80000>;
  202. read-only;
  203. };
  204. partition@c80000 {
  205. label = "0:cdt_1";
  206. reg = <0xc80000 0x80000>;
  207. read-only;
  208. };
  209. partition@d00000 {
  210. label = "0:appsblenv";
  211. reg = <0xd00000 0x80000>;
  212. };
  213. partition@d80000 {
  214. label = "0:appsbl";
  215. reg = <0xd80000 0x100000>;
  216. read-only;
  217. };
  218. partition@e80000 {
  219. label = "0:appsbl_1";
  220. reg = <0xe80000 0x100000>;
  221. read-only;
  222. };
  223. partition@f80000 {
  224. label = "0:art";
  225. reg = <0xf80000 0x80000>;
  226. read-only;
  227. nvmem-layout {
  228. compatible = "fixed-layout";
  229. #address-cells = <1>;
  230. #size-cells = <1>;
  231. macaddr_dp1: macaddr@0 {
  232. reg = <0x0 0x6>;
  233. };
  234. macaddr_dp2: macaddr@6 {
  235. reg = <0x6 0x6>;
  236. };
  237. macaddr_dp3: macaddr@c {
  238. reg = <0xc 0x6>;
  239. };
  240. macaddr_dp4: macaddr@12 {
  241. reg = <0x12 0x6>;
  242. };
  243. macaddr_dp5: macaddr@18 {
  244. reg = <0x18 0x6>;
  245. };
  246. caldata_qca9889: caldata@4d000 {
  247. reg = <0x4d000 0x844>;
  248. };
  249. };
  250. };
  251. partition@1000000 {
  252. label = "bdata";
  253. reg = <0x1000000 0x80000>;
  254. };
  255. partition@1080000 {
  256. /* This is crash + crash_syslog parts combined */
  257. label = "pstore";
  258. reg = <0x1080000 0x100000>;
  259. };
  260. partition@1180000 {
  261. label = "ubi_kernel";
  262. reg = <0x1180000 0x3800000>;
  263. };
  264. partition@4980000 {
  265. label = "rootfs";
  266. reg = <0x4980000 0xb680000>;
  267. };
  268. };
  269. };
  270. };
  271. &qusb_phy_0 {
  272. status = "okay";
  273. };
  274. &ssphy_0 {
  275. status = "okay";
  276. };
  277. &usb_0 {
  278. status = "okay";
  279. };
  280. &mdio {
  281. status = "okay";
  282. pinctrl-0 = <&mdio_pins>;
  283. pinctrl-names = "default";
  284. reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
  285. ethernet-phy-package@0 {
  286. #address-cells = <1>;
  287. #size-cells = <0>;
  288. compatible = "qcom,qca8075-package";
  289. reg = <0>;
  290. qcom,package-mode = "qsgmii";
  291. qca8075_0: ethernet-phy@0 {
  292. compatible = "ethernet-phy-ieee802.3-c22";
  293. reg = <0>;
  294. leds {
  295. #address-cells = <1>;
  296. #size-cells = <0>;
  297. led@0 {
  298. reg = <0>;
  299. color = <LED_COLOR_ID_GREEN>;
  300. function = LED_FUNCTION_LAN;
  301. default-state = "keep";
  302. };
  303. };
  304. };
  305. qca8075_1: ethernet-phy@1 {
  306. compatible = "ethernet-phy-ieee802.3-c22";
  307. reg = <1>;
  308. leds {
  309. #address-cells = <1>;
  310. #size-cells = <0>;
  311. led@0 {
  312. reg = <0>;
  313. color = <LED_COLOR_ID_GREEN>;
  314. function = LED_FUNCTION_LAN;
  315. default-state = "keep";
  316. };
  317. };
  318. };
  319. qca8075_2: ethernet-phy@2 {
  320. compatible = "ethernet-phy-ieee802.3-c22";
  321. reg = <2>;
  322. leds {
  323. #address-cells = <1>;
  324. #size-cells = <0>;
  325. led@0 {
  326. reg = <0>;
  327. color = <LED_COLOR_ID_GREEN>;
  328. function = LED_FUNCTION_LAN;
  329. default-state = "keep";
  330. };
  331. };
  332. };
  333. qca8075_3: ethernet-phy@3 {
  334. compatible = "ethernet-phy-ieee802.3-c22";
  335. reg = <3>;
  336. leds {
  337. #address-cells = <1>;
  338. #size-cells = <0>;
  339. led@0 {
  340. reg = <0>;
  341. color = <LED_COLOR_ID_GREEN>;
  342. function = LED_FUNCTION_LAN;
  343. default-state = "keep";
  344. };
  345. };
  346. };
  347. };
  348. qca8081: ethernet-phy@24 {
  349. compatible = "ethernet-phy-id004d.d101";
  350. reg = <24>;
  351. reset-deassert-us = <10000>;
  352. reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  353. leds {
  354. #address-cells = <1>;
  355. #size-cells = <0>;
  356. led@0 {
  357. reg = <0>;
  358. color = <LED_COLOR_ID_GREEN>;
  359. function = LED_FUNCTION_WAN;
  360. default-state = "keep";
  361. };
  362. };
  363. };
  364. };
  365. &switch {
  366. status = "okay";
  367. switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
  368. switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
  369. switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
  370. switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance1*/
  371. qcom,port_phyinfo {
  372. port@1 {
  373. port_id = <1>;
  374. phy_address = <0>;
  375. };
  376. port@2 {
  377. port_id = <2>;
  378. phy_address = <1>;
  379. };
  380. port@3 {
  381. port_id = <3>;
  382. phy_address = <2>;
  383. };
  384. port@4 {
  385. port_id = <4>;
  386. phy_address = <3>;
  387. };
  388. port@5 {
  389. port_id = <5>;
  390. phy_address = <24>;
  391. port_mac_sel = "QGMAC_PORT";
  392. };
  393. };
  394. };
  395. &edma {
  396. status = "okay";
  397. };
  398. &dp1 {
  399. status = "okay";
  400. phy-mode = "qsgmii";
  401. phy-handle = <&qca8075_0>;
  402. label = "lan4";
  403. nvmem-cells = <&macaddr_dp1>;
  404. nvmem-cell-names = "mac-address";
  405. };
  406. &dp2 {
  407. status = "okay";
  408. phy-mode = "qsgmii";
  409. phy-handle = <&qca8075_1>;
  410. label = "lan3";
  411. nvmem-cells = <&macaddr_dp2>;
  412. nvmem-cell-names = "mac-address";
  413. };
  414. &dp3 {
  415. status = "okay";
  416. phy-mode = "qsgmii";
  417. phy-handle = <&qca8075_2>;
  418. label = "lan2";
  419. nvmem-cells = <&macaddr_dp3>;
  420. nvmem-cell-names = "mac-address";
  421. };
  422. &dp4 {
  423. status = "okay";
  424. phy-mode = "qsgmii";
  425. phy-handle = <&qca8075_3>;
  426. label = "lan1";
  427. nvmem-cells = <&macaddr_dp4>;
  428. nvmem-cell-names = "mac-address";
  429. };
  430. &dp5 {
  431. status = "okay";
  432. phy-mode = "sgmii";
  433. phy-handle = <&qca8081>;
  434. label = "wan";
  435. nvmem-cells = <&macaddr_dp5>;
  436. nvmem-cell-names = "mac-address";
  437. };
  438. &pcie_qmp0 {
  439. status = "okay";
  440. };
  441. &pcie0 {
  442. status = "okay";
  443. perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
  444. bridge@0,0 {
  445. reg = <0x00000000 0 0 0 0>;
  446. #address-cells = <3>;
  447. #size-cells = <2>;
  448. ranges;
  449. wifi@1,0 {
  450. status = "okay";
  451. /* ath11k has no DT compatible for PCI cards */
  452. compatible = "pci17cb,1104";
  453. reg = <0x00010000 0 0 0 0>;
  454. qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
  455. };
  456. };
  457. };
  458. &pcie_qmp1 {
  459. status = "okay";
  460. };
  461. &pcie1 {
  462. status = "okay";
  463. perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
  464. bridge@1,0 {
  465. reg = <0x00010000 0 0 0 0>;
  466. #address-cells = <3>;
  467. #size-cells = <2>;
  468. ranges;
  469. wifi@1,0 {
  470. status = "okay";
  471. compatible = "qcom,ath10k";
  472. reg = <0x00010000 0 0 0 0>;
  473. qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
  474. nvmem-cell-names = "calibration";
  475. nvmem-cells = <&caldata_qca9889>;
  476. };
  477. };
  478. };
  479. &wifi {
  480. status = "okay";
  481. qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
  482. };