mt7986a-tplink-tl-xdr-common.dtsi 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/leds/common.h>
  5. #include "mt7986a.dtsi"
  6. / {
  7. aliases {
  8. serial0 = &uart0;
  9. label-mac-device = &gmac0;
  10. led-boot = &led_status_green;
  11. led-failsafe = &led_status_red;
  12. led-running = &led_status_green;
  13. led-upgrade = &led_status_red;
  14. };
  15. chosen {
  16. bootargs = "root=/dev/fit0 rootwait";
  17. rootdisk = <&ubi_rootdisk>;
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory {
  21. reg = <0 0x40000000 0 0x20000000>;
  22. };
  23. reg_3p3v: regulator-3p3v {
  24. compatible = "regulator-fixed";
  25. regulator-name = "fixed-3.3V";
  26. regulator-min-microvolt = <3300000>;
  27. regulator-max-microvolt = <3300000>;
  28. regulator-boot-on;
  29. regulator-always-on;
  30. };
  31. reg_5v: regulator-5v {
  32. compatible = "regulator-fixed";
  33. regulator-name = "fixed-5V";
  34. regulator-min-microvolt = <5000000>;
  35. regulator-max-microvolt = <5000000>;
  36. regulator-boot-on;
  37. regulator-always-on;
  38. };
  39. keys {
  40. compatible = "gpio-keys";
  41. reset {
  42. label = "reset";
  43. linux,code = <KEY_RESTART>;
  44. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  45. };
  46. wps {
  47. label = "wps";
  48. linux,code = <KEY_WPS_BUTTON>;
  49. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  50. };
  51. turbo {
  52. label = "turbo";
  53. linux,code = <BTN_1>;
  54. gpios = <&pio 11 GPIO_ACTIVE_LOW>;
  55. };
  56. };
  57. leds {
  58. compatible = "gpio-leds";
  59. led_status_red: status_red {
  60. function = LED_FUNCTION_STATUS;
  61. color = <LED_COLOR_ID_RED>;
  62. gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
  63. };
  64. led_status_green: status_green {
  65. function = LED_FUNCTION_STATUS;
  66. color = <LED_COLOR_ID_GREEN>;
  67. gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
  68. };
  69. turbo {
  70. label = "green:turbo";
  71. gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
  72. };
  73. };
  74. };
  75. &crypto {
  76. status = "okay";
  77. };
  78. &eth {
  79. status = "okay";
  80. gmac0: mac@0 {
  81. compatible = "mediatek,eth-mac";
  82. reg = <0>;
  83. phy-mode = "2500base-x";
  84. nvmem-cells = <&macaddr_config_1c 0>;
  85. nvmem-cell-names = "mac-address";
  86. fixed-link {
  87. speed = <2500>;
  88. full-duplex;
  89. pause;
  90. };
  91. };
  92. gmac1: mac@1 {
  93. compatible = "mediatek,eth-mac";
  94. reg = <1>;
  95. phy-handle = <&phy7>;
  96. phy-mode = "2500base-x";
  97. nvmem-cells = <&macaddr_config_1c 1>;
  98. nvmem-cell-names = "mac-address";
  99. };
  100. mdio: mdio-bus {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. };
  104. };
  105. &mdio {
  106. phy5: ethernet-phy@5 {
  107. compatible = "ethernet-phy-ieee802.3-c45";
  108. reg = <5>;
  109. reset-assert-us = <100000>;
  110. reset-deassert-us = <100000>;
  111. reset-gpios = <&pio 13 GPIO_ACTIVE_LOW>;
  112. realtek,aldps-enable;
  113. };
  114. phy7: ethernet-phy@7 {
  115. compatible = "ethernet-phy-ieee802.3-c45";
  116. reg = <7>;
  117. reset-assert-us = <100000>;
  118. reset-deassert-us = <100000>;
  119. reset-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
  120. realtek,aldps-enable;
  121. };
  122. switch: switch@1f {
  123. compatible = "mediatek,mt7531";
  124. reg = <31>;
  125. reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  126. interrupt-controller;
  127. #interrupt-cells = <1>;
  128. interrupt-parent = <&pio>;
  129. interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  130. };
  131. };
  132. &spi0 {
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&spi_flash_pins>;
  135. status = "okay";
  136. flash@0 {
  137. compatible = "spi-nand";
  138. #address-cells = <1>;
  139. #size-cells = <1>;
  140. reg = <0>;
  141. spi-max-frequency = <20000000>;
  142. spi-tx-bus-width = <4>;
  143. spi-rx-bus-width = <4>;
  144. partitions {
  145. compatible = "fixed-partitions";
  146. #address-cells = <1>;
  147. #size-cells = <1>;
  148. partition@0 {
  149. label = "bl2";
  150. reg = <0x000000 0x0100000>;
  151. read-only;
  152. };
  153. config: partition@100000 {
  154. label = "config";
  155. reg = <0x100000 0x0060000>;
  156. read-only;
  157. nvmem-layout {
  158. compatible = "fixed-layout";
  159. #address-cells = <1>;
  160. #size-cells = <1>;
  161. macaddr_config_1c: macaddr@1c {
  162. compatible = "mac-base";
  163. reg = <0x1c 0x6>;
  164. #nvmem-cell-cells = <1>;
  165. };
  166. };
  167. };
  168. factory: partition@160000 {
  169. label = "factory";
  170. reg = <0x160000 0x0060000>;
  171. read-only;
  172. };
  173. partition@1c0000 {
  174. label = "reserved";
  175. reg = <0x1c0000 0x01c0000>;
  176. read-only;
  177. };
  178. partition@380000 {
  179. label = "fip";
  180. reg = <0x380000 0x0200000>;
  181. read-only;
  182. };
  183. partition@580000 {
  184. compatible = "linux,ubi";
  185. reg = <0x580000 0x7800000>;
  186. label = "ubi";
  187. volumes {
  188. ubi_rootdisk: ubi-volume-fit {
  189. volname = "fit";
  190. };
  191. };
  192. };
  193. };
  194. };
  195. };
  196. &pio {
  197. spi_flash_pins: spi-flash-pins-33-to-38 {
  198. mux {
  199. function = "spi";
  200. groups = "spi0", "spi0_wp_hold";
  201. };
  202. conf-pu {
  203. pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  204. drive-strength = <8>;
  205. mediatek,pull-up-adv = <0>; /* bias-disable */
  206. };
  207. conf-pd {
  208. pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  209. drive-strength = <8>;
  210. mediatek,pull-down-adv = <0>; /* bias-disable */
  211. };
  212. };
  213. };
  214. &ssusb {
  215. vusb33-supply = <&reg_3p3v>;
  216. vbus-supply = <&reg_5v>;
  217. status = "okay";
  218. };
  219. &trng {
  220. status = "okay";
  221. };
  222. &uart0 {
  223. status = "okay";
  224. };
  225. &usb_phy {
  226. status = "okay";
  227. };
  228. &watchdog {
  229. status = "okay";
  230. };
  231. &wifi {
  232. mediatek,mtd-eeprom = <&factory 0x0>;
  233. nvmem-cells = <&macaddr_config_1c 2>;
  234. nvmem-cell-names = "mac-address";
  235. status = "okay";
  236. };