791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch 4.3 KB

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  1. From 813abcd98fb1b2cccf850cdfa092a4bfc50b2363 Mon Sep 17 00:00:00 2001
  2. From: Frank <[email protected]>
  3. Date: Tue, 22 Nov 2022 16:42:32 +0800
  4. Subject: [PATCH] net: phy: add Motorcomm YT8531S phy id.
  5. We added patch for motorcomm.c to support YT8531S. This patch has
  6. been tested on AM335x platform which has one YT8531S interface
  7. card and passed all test cases.
  8. The tested cases indluding: YT8531S UTP function with support of
  9. 10M/100M/1000M; YT8531S Fiber function with support of 100M/1000M;
  10. and YT8531S Combo function that supports auto detection of media type.
  11. Since most functions of YT8531S are similar to YT8521 and we reuse some
  12. codes for YT8521 in the patch file.
  13. Signed-off-by: Frank <[email protected]>
  14. Signed-off-by: David S. Miller <[email protected]>
  15. ---
  16. drivers/net/phy/Kconfig | 2 +-
  17. drivers/net/phy/motorcomm.c | 52 +++++++++++++++++++++++++++++++++----
  18. 2 files changed, 48 insertions(+), 6 deletions(-)
  19. --- a/drivers/net/phy/Kconfig
  20. +++ b/drivers/net/phy/Kconfig
  21. @@ -242,7 +242,7 @@ config MOTORCOMM_PHY
  22. tristate "Motorcomm PHYs"
  23. help
  24. Enables support for Motorcomm network PHYs.
  25. - Currently supports the YT8511, YT8521 Gigabit Ethernet PHYs.
  26. + Currently supports the YT8511, YT8521, YT8531S Gigabit Ethernet PHYs.
  27. config NATIONAL_PHY
  28. tristate "National Semiconductor PHYs"
  29. --- a/drivers/net/phy/motorcomm.c
  30. +++ b/drivers/net/phy/motorcomm.c
  31. @@ -1,6 +1,6 @@
  32. // SPDX-License-Identifier: GPL-2.0+
  33. /*
  34. - * Motorcomm 8511/8521 PHY driver.
  35. + * Motorcomm 8511/8521/8531S PHY driver.
  36. *
  37. * Author: Peter Geis <[email protected]>
  38. * Author: Frank <[email protected]>
  39. @@ -12,9 +12,10 @@
  40. #include <linux/phy.h>
  41. #define PHY_ID_YT8511 0x0000010a
  42. -#define PHY_ID_YT8521 0x0000011A
  43. +#define PHY_ID_YT8521 0x0000011A
  44. +#define PHY_ID_YT8531S 0x4F51E91A
  45. -/* YT8521 Register Overview
  46. +/* YT8521/YT8531S Register Overview
  47. * UTP Register space | FIBER Register space
  48. * ------------------------------------------------------------
  49. * | UTP MII | FIBER MII |
  50. @@ -147,7 +148,7 @@
  51. #define YT8521_LINK_TIMER_CFG2_REG 0xA5
  52. #define YT8521_LTCR_EN_AUTOSEN BIT(15)
  53. -/* 0xA000, 0xA001, 0xA003 ,and 0xA006 ~ 0xA00A are common ext registers
  54. +/* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers
  55. * of yt8521 phy. There is no need to switch reg space when operating these
  56. * registers.
  57. */
  58. @@ -221,6 +222,9 @@
  59. */
  60. #define YTPHY_WCR_TYPE_PULSE BIT(0)
  61. +#define YT8531S_SYNCE_CFG_REG 0xA012
  62. +#define YT8531S_SCR_SYNCE_ENABLE BIT(6)
  63. +
  64. /* Extended Register end */
  65. struct yt8521_priv {
  66. @@ -648,6 +652,26 @@ static int yt8521_probe(struct phy_devic
  67. }
  68. /**
  69. + * yt8531s_probe() - read chip config then set suitable polling_mode
  70. + * @phydev: a pointer to a &struct phy_device
  71. + *
  72. + * returns 0 or negative errno code
  73. + */
  74. +static int yt8531s_probe(struct phy_device *phydev)
  75. +{
  76. + int ret;
  77. +
  78. + /* Disable SyncE clock output by default */
  79. + ret = ytphy_modify_ext_with_lock(phydev, YT8531S_SYNCE_CFG_REG,
  80. + YT8531S_SCR_SYNCE_ENABLE, 0);
  81. + if (ret < 0)
  82. + return ret;
  83. +
  84. + /* same as yt8521_probe */
  85. + return yt8521_probe(phydev);
  86. +}
  87. +
  88. +/**
  89. * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
  90. * @phydev: a pointer to a &struct phy_device
  91. *
  92. @@ -1750,11 +1774,28 @@ static struct phy_driver motorcomm_phy_d
  93. .suspend = yt8521_suspend,
  94. .resume = yt8521_resume,
  95. },
  96. + {
  97. + PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
  98. + .name = "YT8531S Gigabit Ethernet",
  99. + .get_features = yt8521_get_features,
  100. + .probe = yt8531s_probe,
  101. + .read_page = yt8521_read_page,
  102. + .write_page = yt8521_write_page,
  103. + .get_wol = ytphy_get_wol,
  104. + .set_wol = ytphy_set_wol,
  105. + .config_aneg = yt8521_config_aneg,
  106. + .aneg_done = yt8521_aneg_done,
  107. + .config_init = yt8521_config_init,
  108. + .read_status = yt8521_read_status,
  109. + .soft_reset = yt8521_soft_reset,
  110. + .suspend = yt8521_suspend,
  111. + .resume = yt8521_resume,
  112. + },
  113. };
  114. module_phy_driver(motorcomm_phy_drvs);
  115. -MODULE_DESCRIPTION("Motorcomm 8511/8521 PHY driver");
  116. +MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver");
  117. MODULE_AUTHOR("Peter Geis");
  118. MODULE_AUTHOR("Frank");
  119. MODULE_LICENSE("GPL");
  120. @@ -1762,6 +1803,7 @@ MODULE_LICENSE("GPL");
  121. static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
  122. { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
  123. { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
  124. + { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
  125. { /* sentinal */ }
  126. };