0053-net-dsa-mediatek-add-software-phy-polling.patch 1.8 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768
  1. From 53eec2c3580e63fdebfc25ae324f30cd8aa4403b Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Thu, 10 Aug 2017 16:00:46 +0200
  4. Subject: [PATCH 53/57] net: dsa: mediatek: add software phy polling
  5. Signed-off-by: John Crispin <[email protected]>
  6. ---
  7. drivers/net/dsa/mt7530.c | 38 ++++++++++++++++++++++++++++++++++++++
  8. drivers/net/dsa/mt7530.h | 1 +
  9. 2 files changed, 39 insertions(+)
  10. --- a/drivers/net/dsa/mt7530.c
  11. +++ b/drivers/net/dsa/mt7530.c
  12. @@ -728,6 +728,44 @@ static void mt7530_adjust_link(struct ds
  13. * all finished.
  14. */
  15. mt7623_pad_clk_setup(ds);
  16. + } else {
  17. + u16 lcl_adv = 0, rmt_adv = 0;
  18. + u8 flowctrl;
  19. + u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
  20. +
  21. + switch (phydev->speed) {
  22. + case SPEED_1000:
  23. + mcr |= PMCR_FORCE_SPEED_1000;
  24. + break;
  25. + case SPEED_100:
  26. + mcr |= PMCR_FORCE_SPEED_100;
  27. + break;
  28. + };
  29. +
  30. + if (phydev->link)
  31. + mcr |= PMCR_FORCE_LNK;
  32. +
  33. + if (phydev->duplex) {
  34. + mcr |= PMCR_FORCE_FDX;
  35. +
  36. + if (phydev->pause)
  37. + rmt_adv = LPA_PAUSE_CAP;
  38. + if (phydev->asym_pause)
  39. + rmt_adv |= LPA_PAUSE_ASYM;
  40. +
  41. + if (phydev->advertising & ADVERTISED_Pause)
  42. + lcl_adv |= ADVERTISE_PAUSE_CAP;
  43. + if (phydev->advertising & ADVERTISED_Asym_Pause)
  44. + lcl_adv |= ADVERTISE_PAUSE_ASYM;
  45. +
  46. + flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  47. +
  48. + if (flowctrl & FLOW_CTRL_TX)
  49. + mcr |= PMCR_TX_FC_EN;
  50. + if (flowctrl & FLOW_CTRL_RX)
  51. + mcr |= PMCR_RX_FC_EN;
  52. + }
  53. + mt7530_write(priv, MT7530_PMCR_P(port), mcr);
  54. }
  55. }
  56. --- a/drivers/net/dsa/mt7530.h
  57. +++ b/drivers/net/dsa/mt7530.h
  58. @@ -155,6 +155,7 @@ enum mt7530_stp_state {
  59. #define PMCR_TX_FC_EN BIT(5)
  60. #define PMCR_RX_FC_EN BIT(4)
  61. #define PMCR_FORCE_SPEED_1000 BIT(3)
  62. +#define PMCR_FORCE_SPEED_100 BIT(2)
  63. #define PMCR_FORCE_FDX BIT(1)
  64. #define PMCR_FORCE_LNK BIT(0)
  65. #define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \