033-v6.0-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patchgit 4.3 KB

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  1. From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
  2. From: William Zhang <[email protected]>
  3. Date: Wed, 8 Jun 2022 11:00:59 -0700
  4. Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146
  5. Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
  6. SoC description DTS header and bcm963146.dts is a simple DTS file for
  7. Broadcom BCM963146 Reference board that only enable the UART port.
  8. Signed-off-by: William Zhang <[email protected]>
  9. Signed-off-by: Florian Fainelli <[email protected]>
  10. ---
  11. arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
  12. .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 110 ++++++++++++++++++
  13. .../boot/dts/broadcom/bcmbca/bcm963146.dts | 30 +++++
  14. 3 files changed, 142 insertions(+), 1 deletion(-)
  15. create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
  16. create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
  17. --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  18. +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  19. @@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
  20. bcm4912-asus-gt-ax6000.dtb \
  21. bcm94912.dtb \
  22. bcm963158.dtb \
  23. - bcm96858.dtb
  24. + bcm96858.dtb \
  25. + bcm963146.dtb
  26. --- /dev/null
  27. +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
  28. @@ -0,0 +1,110 @@
  29. +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  30. +/*
  31. + * Copyright 2022 Broadcom Ltd.
  32. + */
  33. +
  34. +#include <dt-bindings/interrupt-controller/irq.h>
  35. +#include <dt-bindings/interrupt-controller/arm-gic.h>
  36. +
  37. +/ {
  38. + compatible = "brcm,bcm63146", "brcm,bcmbca";
  39. + #address-cells = <2>;
  40. + #size-cells = <2>;
  41. +
  42. + interrupt-parent = <&gic>;
  43. +
  44. + cpus {
  45. + #address-cells = <2>;
  46. + #size-cells = <0>;
  47. +
  48. + B53_0: cpu@0 {
  49. + compatible = "brcm,brahma-b53";
  50. + device_type = "cpu";
  51. + reg = <0x0 0x0>;
  52. + next-level-cache = <&L2_0>;
  53. + enable-method = "psci";
  54. + };
  55. +
  56. + B53_1: cpu@1 {
  57. + compatible = "brcm,brahma-b53";
  58. + device_type = "cpu";
  59. + reg = <0x0 0x1>;
  60. + next-level-cache = <&L2_0>;
  61. + enable-method = "psci";
  62. + };
  63. +
  64. + L2_0: l2-cache0 {
  65. + compatible = "cache";
  66. + };
  67. + };
  68. +
  69. + timer {
  70. + compatible = "arm,armv8-timer";
  71. + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  72. + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  73. + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  74. + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  75. + };
  76. +
  77. + pmu: pmu {
  78. + compatible = "arm,cortex-a53-pmu";
  79. + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  80. + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  81. + interrupt-affinity = <&B53_0>, <&B53_1>;
  82. + };
  83. +
  84. + clocks: clocks {
  85. + periph_clk: periph-clk {
  86. + compatible = "fixed-clock";
  87. + #clock-cells = <0>;
  88. + clock-frequency = <200000000>;
  89. + };
  90. + uart_clk: uart-clk {
  91. + compatible = "fixed-factor-clock";
  92. + #clock-cells = <0>;
  93. + clocks = <&periph_clk>;
  94. + clock-div = <4>;
  95. + clock-mult = <1>;
  96. + };
  97. + };
  98. +
  99. + psci {
  100. + compatible = "arm,psci-0.2";
  101. + method = "smc";
  102. + };
  103. +
  104. + axi@81000000 {
  105. + compatible = "simple-bus";
  106. + #address-cells = <1>;
  107. + #size-cells = <1>;
  108. + ranges = <0x0 0x0 0x81000000 0x8000>;
  109. +
  110. + gic: interrupt-controller@1000 {
  111. + compatible = "arm,gic-400";
  112. + #interrupt-cells = <3>;
  113. + interrupt-controller;
  114. + reg = <0x1000 0x1000>,
  115. + <0x2000 0x2000>,
  116. + <0x4000 0x2000>,
  117. + <0x6000 0x2000>;
  118. + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  119. + IRQ_TYPE_LEVEL_HIGH)>;
  120. + };
  121. + };
  122. +
  123. + bus@ff800000 {
  124. + compatible = "simple-bus";
  125. + #address-cells = <1>;
  126. + #size-cells = <1>;
  127. + ranges = <0x0 0x0 0xff800000 0x800000>;
  128. +
  129. + uart0: serial@12000 {
  130. + compatible = "arm,pl011", "arm,primecell";
  131. + reg = <0x12000 0x1000>;
  132. + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  133. + clocks = <&uart_clk>, <&uart_clk>;
  134. + clock-names = "uartclk", "apb_pclk";
  135. + status = "disabled";
  136. + };
  137. + };
  138. +};
  139. --- /dev/null
  140. +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
  141. @@ -0,0 +1,30 @@
  142. +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  143. +/*
  144. + * Copyright 2022 Broadcom Ltd.
  145. + */
  146. +
  147. +/dts-v1/;
  148. +
  149. +#include "bcm63146.dtsi"
  150. +
  151. +/ {
  152. + model = "Broadcom BCM963146 Reference Board";
  153. + compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
  154. +
  155. + aliases {
  156. + serial0 = &uart0;
  157. + };
  158. +
  159. + chosen {
  160. + stdout-path = "serial0:115200n8";
  161. + };
  162. +
  163. + memory@0 {
  164. + device_type = "memory";
  165. + reg = <0x0 0x0 0x0 0x08000000>;
  166. + };
  167. +};
  168. +
  169. +&uart0 {
  170. + status = "okay";
  171. +};